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Frequent questions

  • [FAQ] How to synchronize the PRU IEP timer with Linux system time?

    I am using a Sitara processor with a Linux core, a time sync router, and a PRU subsystem (AM62x, AM64x, AM65x). I want to synchronize the Linux system time with an IEP timer in the PRU subsystem. How do I do it? We will use AM64x for this example, but…

  • [FAQ] PROCESSOR-SDK-J7200: How to change/generate the “Eth” configuration for MCAL Ethernet Application from one core to other core.

    Part Number: PROCESSOR-SDK-J7200 Other Parts Discussed in Thread: DRA821 , DRA829 , SYSCONFIG How to change/generate the “Eth” configuration for MCAL Ethernet Application from one core to other core.

  • [FAQ] AM6412: AM64x SoC power supply slew control for 3.3V_SYS using load switch

    Part Number: AM6412 Other Parts Discussed in Thread: TPS65219 Hi team, I'm helping my customer design the power part of AM64. For the power supply slew rate control part, it says the slew rate should be controlled under 18mV/us. How should we set…

  • [FAQ] Redundant boot from eMMC boot partitions on AM62x

    1. booting from eMMC boot partition vs UDA partition It is recommended to use eMMC boot partition for user's BootLoader (BL) - eMMC boot partition is designed for bootloader user case - it is possible to write-protect boot0/boot1 as necessary - eMMC boot…

  • [FAQ] AM62A3: Any way to get 2 eMMC interfaces?

    Part Number: AM62A3 Hello, Using the AM62A, is there any way to implement two eMMC interfaces? The device has 3 MMC interfaces but the datasheet only shows MMC0 supporting eMMC. We really need a way to get 2 so I'll ask a couple questions from someone…

  • [FAQ] PROCESSOR-SDK-TDAX: How to change input display pipeline in the DSS M2M WB node?

    Part Number: PROCESSOR-SDK-TDAX The patches shared on below link adds support for DSS memory to memory path in the vision apps and TIOVX. These patches are also integrated SDK8.6. By default, this patch uses VIDL2 pipeline as input pipeline and WB pipeline…

  • [FAQ] TDA4VM: Process OpenVX Graph while simultaneously configuring a camera

    Part Number: TDA4VM How to configure a camera without affecting the OpenVX graph, while the single cam application graph is running

  • [FAQ] AM6442, AM6441, AM6422, AM6421, AM6412, AM6411 and AM2434, AM2432, AM2431 (ALV, ALX) Custom board hardware design – Queries regarding Crystal selection and clock specifications

    Part Number: AM6442 AM2432 AM6411 AM2431 AM6422 AM6412 AM6421 AM2434 AM6441 Other Parts Discussed in Thread: TMDS64EVM , AM6442 , AM3352 , AM62A3-Q1 , AM62L , OMAP-L138 , AM62A7 Hi TI Experts, I have the below queries regarding the crystal selection…

  • [FAQ] AM6442, AM6441, AM6422, AM6421, AM6412, AM6411 and AM2434, AM2432, AM2431 (ALV, ALX) Custom board hardware design – I2C interface

    Part Number: AM6442 Other Parts Discussed in Thread: AM62A7 , AM6412 , AM6422 , , AM2434 , AM62P , SK-AM64B Hi TI Experts, I have the below queries regarding the I2C interface: Need information on the number of I2C interfaces available Termination…

  • [FAQ] AM623: Does AM62x support two 4GB DDR?

    Part Number: AM623 Hi, TI Partner Follow data sheet. it describe as below. DDR Subsystem (DDRSS) – Supports LPDDR4, DDR4 memory types – 16-Bit data bus with inline ECC – Supports speeds up to 1600 MT/s – Max addressable range • 8GBytes with DDR4…

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