https://e2e.ti.com/support/processors-group/processors/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1635903/tda4aen-q1-simulating-a-speed-grade-j-on-a-k-grade-tda4-device/6402920Thu, 02 Jul 2026 11:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:773f585c-8a6d-4b1c-960d-c88f94c368b3G&#246;tz FriedrichHello Keerthy and Kyle, we need to find a solution soon. Please let us know when you need additional information from our side. Best regards, G&#246;tzhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1660505/am625-q1-disable-dss-gpu-in-software/6402884Thu, 02 Jul 2026 11:36:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bd30ed8e-3502-4aad-8139-b0768fae2b55Bin LiuHi, Your query has been routed to our Linux expert for comments.https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1660661/am62l-evse-dev-evm-no-wl1837-module-responseThu, 02 Jul 2026 11:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c70313e3-11c4-4b91-acd4-dd706ae37077Mariusz BarnasPart Number: AM62L-EVSE-DEV-EVM Other Parts Discussed in Thread: WL1837 , SK-AM62 Dear All, For several days now, we&#39;ve been trying to get communication working on our recently purchased EVM SK-AM62, an AM62x starter kit for Sitara™ processors. The HDMI and LCD outputs are enabled via LVDS, and after hardware changes, the touchpanel also works. Unfortunately, we&#39;re unable to get the WL1837 module to work. The module doesn&#39;t respond via CMD or IRQ. It receives the correct power sequence: a slow CLK of 32kHz, followed by raising the WLAN_EN state. MMC2_CLK 400kHz is present, along with packets sent to MMC2_CMD by the host. There&#39;s no activity on WLAN_IRQ (fixed 1.8V) and no responses to MMC2_CMD. As part of our testing, we decided to desolder resistor R6 PU to VCC1_8 WLAN_IRQ. Voltage monitoring shows a floating reading of about 0.4V. Tests involving setting the AM62 MMC2_SDWP B23 pin as an output and forcing voltage control on the desoldered R6 resistor pad yielded no results. It&#39;s as if there were no physical connection between the MCU and the WL1837 via WLAN_IRQ. Hence the question: has the EVM been tested for communication with the WL1837? What can you advise in this situation? Kind regards, MariuszAM62L-EVSE-DEV-EVMSK-AM62WL1837https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1657235/tms320c50-emu5x-programmierung/6402853Thu, 02 Jul 2026 10:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f315b05b-847f-40d7-90a5-3ee9afc40fadCarsten EugenHello I have a answer from my technical colleague: We have an old CodeComposer V4.1 Service Pack 1 in use to flash boards with TMS320C30 JTAG Pod XDS-510 is available Binary files for TMS320C50 are available On a different old board, we have to flash the two TMS320C50. We need the Add-On, to enable the CodeComposer to handle the TMS320C50 processors, which operate on a common Flash-PROM. Thank you for your feedback. Best regards Carsten Eugenhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1660649/am620-q1-compatibility-with-lpddr4-w66bp6nbuafk-from-winbondThu, 02 Jul 2026 10:49:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c7e6df32-c78c-4fb6-ab6c-b1e3eedbc30cTil SchoengarthPart Number: AM620-Q1 Hi team, do you have any experience with above DDR4 together with our Sitara SoCs? Maybe some customer used this combination in the past or we have done testing ourselves? Best regards, TilInfotainment &amp; ClusterAM620-Q1https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1655811/am6421-am6421-configuration-pcie-ep-trm-information-missing/6402843Thu, 02 Jul 2026 10:49:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ef5e4499-2b3a-4b66-bb72-61a3338c3be5Thomas DorschHi Tushar, it looks promising now. With your modified file, I have memory read/write access to configured BAR0 of Pcie EP on AM64. Thank you very much. One more point is, that the PCI Link only reaches PCIE_GEN1 and not GEN2. I&#39;m not sure yet, if this is also pci driver problem on AM64 side. Should I open for this a new topic? Best regards, Thomashttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1657273/j722sxh01evm-pbist-memory-in-sbl/6402829Thu, 02 Jul 2026 10:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b761b240-4cf2-4a91-947b-b4f0112ca375Chen JieHi Josiitaa, Thank you for your support. Regards, Chenhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1660647/j722sxh01evm-guidance-on-downgrading-from-processor-sdk-linux-11-01-00-03-to-11-00-00-08-for-camera-bring-upThu, 02 Jul 2026 10:27:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2ec08332-93a9-4939-abde-ab3017479ebaARUN SPart Number: J722SXH01EVM Hi, We are currently using Processor SDK Linux 11.01.00.03 on the J722S platform. We have modified the camera drivers and Device Tree files to bring up our camera module. The camera supports both RGB and IR streaming, and after our modifications we are able to access the streams through separate V4L2 video nodes ( /dev/video3 for RGB and /dev/video4 for IR). Our third-party vendor is using Processor SDK Linux 11.00.00.08 , so we are planning to downgrade our development environment from 11.01.00.03 to 11.00.00.08 to maintain compatibility. We would like to know if there are any known compatibility issues or limitations when moving from SDK 11.01.00.03 to 11.00.00.08 , particularly with respect to the camera subsystem, CSI-2 pipeline, media framework, or V4L2. Is there any possibility that the multiple video node setup (RGB on /dev/video3 and IR on /dev/video4 ) may not work as expected on SDK 11.00.00.08 , or are there any driver or Device Tree changes that we should be aware of before performing the downgrade? Any guidance or recommendations would be appreciated. Thank you.J722SXH01EVMhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1659819/am62p-lvds-bringup-in-am62p5-evk-android-sdk/6402816Thu, 02 Jul 2026 10:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4af9e2f4-c3f9-4981-9e6c-9ec62b2ac451Divyansh MittalHey, Can you please check if the following commit is already there in your source? specifically the oldi-io-ctrl part? https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/commit/arch/arm64/boot/dts/ti?h=ti-android-linux-6.12.y&amp;id=15eeeb6cf2cf81d19976069de54b8b1ed48730eahttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1657008/am6442-can-t-set-clock-of-wwdt-rti-on-a53-core/6402806Thu, 02 Jul 2026 10:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2b2ba4c2-db8b-4f00-99b5-2faa7bf7e445Taro TakedaHello Anil, One last question, please. Is the fact that interrupts don’t trigger on the A53 core when the RTI clock is set to 25 MHz a software issue? Or is it an SoC issue? Regards, TAKEDA Tarohttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1657273/j722sxh01evm-pbist-memory-in-sbl/6402805Thu, 02 Jul 2026 10:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7f44261a-f735-435b-b7dc-1242b9127a31Josiitaa RLHi, We are able to reproduce this issue. I have raised an internal bug to fix it. It is expected in the SDK release 11.2.2 in September. JIRA ID for internal tracking: jira.itg.ti.com/.../PROC_SDL-10028 Regards, Josiitaahttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1659260/tda4vm-j721e-aadapt-secure-boot-on-the-gp-board-for-sbl-and-system-firmware/6402791Thu, 02 Jul 2026 09:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3a3accba-5da5-4b68-9281-1955384fa677Baby Sarath Sasidharan NairHi Diwakar, When reviewing your recent comment along side the previous clarification (copied below), I am confused regarding the use of the customer key. . In other words, hash validation is skipped for binaries signed with any key except the RSA degenerate (dummy) key. Could you kindly check this as well. Regards, Sarathhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1659761/am2431-qspi-sbl-firmware-read-slow/6402774Thu, 02 Jul 2026 09:47:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:cd355dd6-35df-4220-be67-b9e6f8710166Vaibhav Kumar[quote userid=&quot;668281&quot; url=&quot;~/support/processors-group/processors/f/processors-forum/1659761/am2431-qspi-sbl-firmware-read-slow/6402310&quot;]Flash: Renesas 32MBit SPI/QSP[/quote] Hi, Could you share the exact Flash Part Datasheet? If it is confidential, then you can share it to me via email/webex and not over this forum. Also, the datasheet is required, for us to check the maximum frequency the flash supports and then we can see what else can be done to improve the clock frequency. Can you tell us the frequency(if you have a logic analyzer) of when the ROM reads the Bootloader? I believe when the bootloader is loading the appimage the observed frequency at your end is 4 MHz, what about when the ROM is reading the bootloader? Regards, Vaibhavhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1657355/am5726-a15-domain-lockup-after-several-days/6402773Thu, 02 Jul 2026 09:47:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8178bcfd-9033-4c38-8311-87c308d0ff09Rasty SlutskerRichard Woodruff I have another interesting finding. No Linux, plain RTOS, single A15.0 core. With help is AI I created a script that runs L3 diagnostics and I found that L3 complains about GPMC. No lockup just compian. Fortunately I was able to wrap EVERY GPMC read/write access with probe like below #define L3_GPMC_STDERRLOG_MAIN (*(volatile uint32_t *)0x44000148u) extern int gpmc_cnt; static inline void GpmcTrapIfL3Error(void) { if (L3_GPMC_STDERRLOG_MAIN != 0u) { for (;;) { /* Break here and inspect backtrace */ } } gpmc_cnt++; } Access counter grows to 60K. before I catch it. It is always the same pattern - always reading the some counter from GPMC/FPGA in ISR. Does it tell some story? Thanks Rasty AI summary (may be helpfull) Syntax memu32[0][0x4A008E28] - r/w access of memory via commmand line interface (UART or Socket) Subject: AM5726 A15/MPU GPMC read causes persistent L3 custom error We are investigating an intermittent A15 cluster lockup on AM5726. DSP remains alive and can access system registers over UART. After enabling A15 CoreSight debug access: memu32[0][0x4A008E28] = 1 we can read valid A15 CoreSight/DBGPCSR registers: CPU0 DBGPCSR: memu32[0][0x54140084] CPU1 DBGPCSR: memu32[0][0x54142084] CoreSight ID registers are also readable and non-zero, so the debug block is accessible. The L3 NoC error log for the GPMC target reports a persistent error: Target: CLK1 GPMC @ 0x44000100 Registers read: STDERRLOG_MAIN: memu32[0][0x44000148] = 0x00080003 STDERRLOG_HDR: memu32[0][0x4400014C] = 0x00000002 STDERRLOG_MSTADDR: memu32[0][0x44000150] = 0x00000010 STDERRLOG_INFO: memu32[0][0x44000158] = 0x00000000 STDERRLOG_SLVOFSLSB: memu32[0][0x4400015C] = 0x00000000 STDERRLOG_CINFO_INFO: memu32[0][0x44000164] = 0x00000084 STDERRLOG_CINFO_MSTADDR: memu32[0][0x44000168] = 0x00000000 STDERRLOG_CINFO_OPCODE: memu32[0][0x4400016C] = 0x00000002 Decoded meaning: STDERRLOG_MAIN = 0x00080003 bit 0 set: error valid bit 1 set: custom error target: GPMC master: MPU / A15 opcode: Read So the logged condition appears to be: MPU/A15 read transaction to GPMC target generated a GPMC/L3 custom error. Clear behavior: Initial read: memu32[0][0x44000148] = 524291 = 0x00080003 Write back same value: memu32[0][0x44000148] = 524291 Immediate reread: memu32[0][0x44000148] = 3 = 0x00000003 Then write remaining value: memu32[0][0x44000148] = 3 Immediate reread: memu32[0][0x44000148] = 524291 = 0x00080003 This suggests the error is not simply stale; it appears to be re-latched or still active. Board/software context : SoC: AM5726 A15_0: RTOS GPMC FPGA window used by A15 side is mapped at 0x08000000 GPMC accesses are 16-bit register reads/writes Existing GPMC access wrapper is being instrumented to trap immediately after GPMC access if STDERRLOG_MAIN becomes non-zero Questions for TI: What is the exact decode of GPMC L3 custom error: STDERRLOG_MAIN = 0x00080003 CINFO_INFO = 0x00000084 CINFO_OPCODE = 0x00000002 CINFO_MSTADDR = 0x00000000 Can this custom GPMC read error cause the A15/MPU transaction to stall indefinitely or contribute to A15 cluster lockup? Does the L3/GPMC custom error log provide the failing GPMC address or chip-select information? If yes, how should the address be reconstructed from the above registers? What is the recommended way to fully clear this GPMC L3 error condition? Writing back STDERRLOG_MAIN changes 0x00080003 to 0x00000003, but the error later returns to 0x00080003. Are there known errata or required GPMC configuration constraints for AM5726 when MPU/A15 and DSP both access GPMC/FPGA?https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1660473/am625-am625-ccs-load-memory-to-ddr-is-much-slower-than-am3358-with-the-same-xds560v2-setup/6402769Thu, 02 Jul 2026 09:45:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b409c2ad-7d16-4362-9bf7-ddf8065eb8feTushar ThakurHave you tried the same with latest version of CCS? What are the result you got with latest version of CCS? Regards, Tusharhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1655672/j722sxh01evm-tidl-11-02-ptq-cannot-correctly-quantize-sparse-positive-output-distributions-on-j722s/6402768Thu, 02 Jul 2026 09:45:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:91b7ab2f-60e1-4a67-a5dd-6ddd2dc44e7dVarun TripathiIf above doesn&#39;t work, as a baseline, can you also try with &quot; tensor_bits &quot; : 16 and ensure you don&#39;t have issues in your end-end pipeline Thanks, Varunhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1660618/am6421-intermittent-fram-read-corruption-in-mcspi-interrupt-modeThu, 02 Jul 2026 09:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:75d365e9-d910-4a78-9103-9b7541b96190Li JiefeiPart Number: AM6421 Issue Summary We are seeing intermittent FRAM read data corruption on AM64x when using MCSPI in interrupt mode. The issue appears only under system with a higher priority interrupt and mainly affects the tail bytes of non-16-byte-aligned reads. Polling mode does not reproduce this issue in our tests. Platform / Configuration SoC: TI AM64x A53 Interface: MCSPI4 (controller mode) FRAM access via SPI SPI clock: default 25 MHz (also tested at 10 MHz) MCSPI mode: Interrupt mode (issue reproducible), Polling mode (no issue seen) Fifo Trigger Level for RX : 16 or 8 SDK Version : 11_00_00_15 Observed Behavior Intermittent read corruption occurs in interrupt mode. Corruption is concentrated in the last part (tail) of the returned data. Typical symptom: missing/shifted bytes and repeated last byte(s) at the end. In one 104-byte test case (threshold=8), bytes 0x58~0x5F were missed and trailing bytes repeated 0x67 . Intermittent read corruption occurs in interrupt mode. Corruption is concentrated in the last part (tail) of the returned data. Typical symptom: missing/shifted bytes and repeated last byte(s) at the end. In one 104-byte test case (set Fifo Trigger Level for RX= 8), bytes 0x58~0x5F were missed and trailing bytes repeated 0x67. Correct Data read from FRAM at addr 0x100 with length 104 is: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 Error Data read from FRAM at addr 0x100 with length 104 is: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 00 27 00 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 60 61 62 63 64 65 66 67 67 67 67 67 67 67 67 67 End of transfer in logic anlyzer (10M): No higher interupt: With higher interupt: Question to TI Could you please help review whether this behavior is related to any known AM64x MCSPI interrupt-mode limitation/race condition and advise recommended fixes or best-practice configuration for robustness? Let me know if you need any additional logs, waveforms, or test data from our side. Thanks.AM6421Energy infrastructurehttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1660610/am64-pet-calc-am64-pet-v2-pcieThu, 02 Jul 2026 09:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6830844d-cd3f-4fe0-8ef8-3b60da0eebc5Thomas MongellazPart Number: AM64-PET-CALC Hello expert, I&#39;m currently generating a power budget using the AM64_PET_public_Rev2P0 file, and I have a question about the PCIe configuration. According to the datasheet, the AM64xx supports 1x PCIe Gen 2. I wanted to know what 1g, 3g, 5g, 8g, and 10g. 1g : is 1 giga bit per second ? or 1 giga transfert per second ? or 1 giga octet per second ? If my PCIe bandwidth is at 100% on my AM64 (100% 1 lane PCIe GEN2), what should I set it to? Best Regards, ThomasAM64-PET-CALChttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1660603/dra821u-gpt-support-on-dra821Thu, 02 Jul 2026 09:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0fb7e222-6623-4d6f-9f25-b13306e78636P BPart Number: DRA821U Other Parts Discussed in Thread: DRA821 Hi does DRA821 support GPT partition table? Let&#39;s suppose that I would like to partition SD / eMMC using GPT and put all the firmware and software components on such device - will it work or is it somehow not possible due to ROM requirements / limitations? Eg. ROM expects MBR or uses some hardcoded offsets. I&#39;m asking because while browsing through the meta-ti layer I found something like this: // sdimage-2part-efi.wks.in # short-description: Create SD card image with 2 partitions and EFI support # long-description: Creates a partitioned SD card image for TI platforms that # supports EFI. Boot files are located in the first vfat partition with extra # reserved space. We cannot use a GPT here. bootloader --timeout=3 --append=&quot;rootfstype=ext4 ${TI_WKS_BOOTLOADER_APPEND}&quot; part --source bootimg-efi --sourceparams=&quot;loader=${EFI_PROVIDER}&quot; --fstype=vfat --label boot --active --align 1024 --use-uuid --fixed-size 128M part / --source rootfs --fstype=ext4 --label root --align 1024 --use-uuidDRA821DRA821Uhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1655672/j722sxh01evm-tidl-11-02-ptq-cannot-correctly-quantize-sparse-positive-output-distributions-on-j722s/6402720Thu, 02 Jul 2026 09:04:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:33bed86f-2247-4967-b3c1-dd505339a49bSiva Sai Surya YellapuSuggested Mixed Precision Config &quot;advanced_options:output_feature_16bit_names_list&quot; : &quot;/Div_output_0,/model.0/conv/Conv_output_0,/model.0/act/Mul_output_0,/model.1/conv/Conv_output_0,/model.1/act/Mul_output_0,/model.2/cv1/conv/Conv_output_0,/model.2/cv1/act/Mul_output_0,/model.10/cv1/act/Mul_output_0,/model.10/Split_output_0,/model.10/Split_output_1,/model.10/m/m.0/attn/qkv/conv/Conv_output_0,/model.10/m/m.0/attn/Reshape_output_0,/model.10/m/m.0/attn/Split_output_0,/model.10/m/m.0/attn/Split_output_1,/model.10/m/m.0/attn/Split_output_2,/model.10/m/m.0/attn/Transpose_output_0,/model.10/m/m.0/attn/Reshape_2_output_0__5,/model.10/m/m.0/attn/MatMul_output_0,/model.10/m/m.0/attn/Reshape_2_output_0,/model.10/m/m.0/attn/Mul_output_0,/model.10/m/m.0/attn/pe/conv/Conv_output_0,/model.10/m/m.0/attn/Mul_output_0__2,/model.10/m/m.0/attn/Mul_output_0__2__3,/model.10/m/m.0/attn/Softmax_output_0__4,/model.10/m/m.0/attn/Softmax_output_0,/model.10/m/m.0/attn/MatMul_1_output_0,/model.10/m/m.0/attn/Reshape_1_output_0,/model.10/m/m.0/attn/Add_output_0,/model.10/m/m.0/attn/proj/conv/Conv_output_0,/model.10/m/m.0/Add_output_0,/model.10/m/m.0/ffn/ffn.0/conv/Conv_output_0,/model.10/m/m.0/ffn/ffn.0/act/Mul_output_0,/model.10/m/m.0/ffn/ffn.1/conv/Conv_output_0,/model.10/m/m.0/Add_1_output_0,/model.10/Concat_output_0,/cv3.2/cv3.2.2/Conv_output_0,/cv3.1/cv3.1.2/Conv_output_0,/Concat_7_output_0,det_cls_netFormat&quot;, &quot;accuracy_level&quot;:2, Regards, Surya