https://e2e.ti.com/support/processors-group/processors/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1653858/tda4vh-q1-j784s4evm-error-issue-using-dsp-1-3-and-4-in-tiovx/6378815Thu, 11 Jun 2026 06:38:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:03dab432-ed26-486e-94b2-e8214af38e34Gokul SHi Kim, Now the error seems to be in target, can you enable the remote core logs and share here. Run &quot;source ./vision_apps_init.sh&quot; script to enable the remote core logs. Regards, Gokulhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1654114/sk-am62a-lp-issue-with-edgeai-application/6378814Thu, 11 Jun 2026 06:38:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4bd77a1f-c299-4a1d-b7cf-de4774477e46Jay GoyalHi Sajan, Can you please share the complete config that you are trying to run? And I assume this issue is from apps_python in our SDK? If not, please provide which application it is you are trying to run, and if the issue is present with apps_python or apps_cpp as well Regards, Jayhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1650414/am2434-am243-as-communicaiton-module-running-ethercat-stack-met-issue/6378810Thu, 11 Jun 2026 06:36:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:80db582c-40b2-430d-b112-0a2d7e8b7460yijin zhaoPreviously, when testing MII tx clk, it was necessary to set a register and wait for the PRU code to execute for about 2 seconds before writing. Does this register also require this delay?https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1653929/tda4vh-q1-j784s4-watchdog-usage-examples-servicing-reset-configuration-timer-precision/6378795Thu, 11 Jun 2026 06:30:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:27641bf4-d241-4c97-b79c-3f8a7ae063d3AkhilWe are running Linux on A72. Regarding the Main domain reset use case: We are referring section 5.70 in the safety manual.https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1650989/am2432-am243-enhance-link-mode-will-configure-phy-to-power-down-status-and-not-recover/6378792Thu, 11 Jun 2026 06:28:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2f550e7c-d949-4846-9cd4-0a31f7042151Tony TangPHY: YT8255 Application didn&#39;t configure PHY to power down.https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1653893/tda4vm-q1-ethernet-for-custom-tda4vm-board/6378785Thu, 11 Jun 2026 06:22:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:679de951-2f14-4205-8287-dd01cff50e31Tanmay PatilHi, I am assuming that you will be using the standard linux and all the data sources and sinks for ethernet will be in the same OS. In that case, you can do this split. There are different ways to do this based how rigorous you want the data separation and rate limiting to be. But by default it is not an issue to send both the data streams from the same interface. You can put rate limiting on the ssh and scp traffic and let the video stream take the rest of the bandwidth. This is because I am assuming that the video data is realtime and won&#39;t be hogging the entire bandwidth anytime. Are you looking for any hardware based limiting options? Otherwise, you can consider traffic shaping using the tc command on linux. Something like this should be enough for you correct. Regards, Tanmayhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1650414/am2434-am243-as-communicaiton-module-running-ethercat-stack-met-issue/6378773Thu, 11 Jun 2026 06:15:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9d1ca28e-ced9-45b0-8deb-c75b3e06ddb4yijin zhaoFrom the data frame, it could be seen that when there is a problem with mailbox communication, the problematic device requests a safeop status but has not yet requested an OP, is this situation also reasonable? If setting the value of TIESC-PCESS-PATH_TX_DELAY_200_SHZ_COCK to 0x98 have any other effects?https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1653866/am6442-pru_icssg-pru-task-manager-ok-to-sbbo-twice-after-tm_yield_xid/6378745Thu, 11 Jun 2026 05:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ff40b5d2-4c04-4ebe-9a4f-ec829e7b7d9cPratheeshGangadhar[quote userid=&quot;578801&quot; url=&quot;~/support/processors-group/processors/f/processors-forum/1653866/am6442-pru_icssg-pru-task-manager-ok-to-sbbo-twice-after-tm_yield_xid&quot;] xin TM_YIELD_XID, &amp;R0.b3,1 sbbo ... ; save to DRAM sbbo ... ; post to DDR[/quote] Post xin for yield is executed, you have 2 cycles which can be utilized for useful post yield bookkeeping before task manager switches to higher priority task. This is only recommended to fill these 2 cycles. SBBO typically takes 2 cycles to for 4 bytes. One SBBO is fine. SBBO transfer size is 8 bytes, then it needs 3 cycles to complete. Since once PRU executes instruction that needs to complete this will lead to 1 cycle delay in scheduling higher priority task. I would not recommend adding second SBBO in this path.https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1653940/am620-q1-guidance-required-for-ov9284-exposure-and-gain/6378736Thu, 11 Jun 2026 05:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a188009c-85c6-44a2-a070-586305eb8d71Jay GoyalHi Navami, I am assuming this a continuation of the previous thread: AM620-Q1: OV9282 exposure and stobe is not synchronizing I have looked at the updated driver. Here are a few points that I note: 1. The function ov9282_set_strobe doesn&#39;t seem to be called anywhere, so I am assuming you are using that in some other generic driver. 2. The call to enable strobe, using register 0x3009 doesn&#39;t seem to be present in ov9282_update_exp_gain which is the function that any downstream ISP will have access to through V4L2 APIs. [quote userid=&quot;696873&quot; url=&quot;~/support/processors-group/processors/f/processors-forum/1653940/am620-q1-guidance-required-for-ov9284-exposure-and-gain&quot;]How to configure the OV9284 STROBE functionality so that it is automatically synchronized with the sensor exposure timing[/quote] For this, you need to check with the sensor module datasheet. Those would have been shared by the manufacturer of your sensor module. [quote userid=&quot;696873&quot; url=&quot;~/support/processors-group/processors/f/processors-forum/1653940/am620-q1-guidance-required-for-ov9284-exposure-and-gain&quot;]Whether any driver-level modifications are required to achieve automatic exposure-to-STROBE synchronization.[/quote] Other than point 2 in my reply, I don&#39;t think you are missing much. As long as the calculation in ov9282_update_exp_gain, it should be alright. If the functionality is required, the same calculations might also be required as a part of ov9282_set_strobe. [quote userid=&quot;696873&quot; url=&quot;~/support/processors-group/processors/f/processors-forum/1653940/am620-q1-guidance-required-for-ov9284-exposure-and-gain&quot;]The recommended register settings for dynamic exposure and gain control during IR-illuminated night operation[/quote] For these, you need to check with the sensor module vendor. Other than that, you might need an ISP implementation. Here are a few ways you can achieve that: 1. Use a sensor module with built in ISP. 2. Use a software based ISP solution. 3. Switch to a SoC that has an ISP. In Sitara, we have AM62A1 part, which differs from the AM62 in that it has codecs and an ISP, but doesn&#39;t have a GPU. Please see if that is enough for your usecase as well. Regards, Jayhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1653113/j721exsomxevm-j721e-uart-interrupts-not-working-on-mcu3_0-mcu3_1-after-stop-start-via-remoteproc/6378735Thu, 11 Jun 2026 05:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:28e45640-a15e-49b5-b10c-bfd061408e9bVinit PatelHi Anderson, I need more steps, these are just for start and stop of the firmware. What i mean is which boot medias, what applications, how do you boot linux etc... i need all the details of the steps you followed to reproduce on our side. Regards, Vinithttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1653957/tda4ven-q1-wakeup-i2c0-hs-mode-waveform-abnomaly/6378726Thu, 11 Jun 2026 05:45:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:113091e8-b444-403b-8d71-e90be392e99dVinit PatelHi Xie, Allow us some time. We will get back to you ASAP. Thanks for being pateint Vinithttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1653640/tda4vm-stalling-of-m3-core/6378720Thu, 11 Jun 2026 05:42:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:de5afa44-37a4-48f7-8e61-01df931169a8Diwakar DhyaniHi Thomas, Thanks for providing the root cause analysis , will close the issue then if no further question on this topic. Regards Diwakarhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1652987/am62a7-am62a7-evk-boots-only-with-sandisk-64gb-sd-card-other-64gb-128gb-cards-fail/6378710Thu, 11 Jun 2026 05:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c25baa81-8c32-465d-b0ed-19893e28c096Tina Mary PereiraHi , The board booted succesfully when i used this tool. Tried in both Windows and Linuxhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1653485/am263p4-q1-ospi-boot-debug-issue/6378702Thu, 11 Jun 2026 05:30:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4c9fdaf7-a7ba-4b92-aca6-85ff20a25366Nikhil Dasan[quote userid=&quot;703222&quot; url=&quot;~/support/processors-group/processors/f/processors-forum/1653485/am263p4-q1-ospi-boot-debug-issue/6377419&quot;]Flashing the SBL .tiimage into ospi flash by use of CCS tool. Option available inside CCS -&gt; RUN option -&gt; flash project.[/quote] This is incorrect. Can you use the either Uniflash or other flashing tools as mentioned in the SDK documentation to flash the project into the device? AM263Px MCU+ SDK: Flashing Tools Thanks and Regards, Nikhil Dasanhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1652666/j721s2xsomxevm-j721s2-tda4al-dss-output-issue-with-qhd-2560x1440-and-4k-in-single_cam-example-qnx/6378699Thu, 11 Jun 2026 05:27:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d4771354-ae44-4877-85e7-6d5f545f0d0dbonchang kuHi. Takuma i checked dump of both registers and k3conf clocks for 1920x1080 and 2560x1440 setting. the values of resigter of k3conf are totally same between 1920x1080 vs 2560x1440 1. 2560x1440 | 158 | 0 | DEV_DSS0_DSS_FUNC_CLK | CLK_STATE_READY | 600000000 | | 158 | 1 | DEV_DSS0_DSS_INST0_DPI_0_IN_CLK | CLK_STATE_READY | 74250000 | | 158 | 2 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK | CLK_STATE_READY | 148500000 | | 158 | 3 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 148500000 | | 158 | 4 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0 | CLK_STATE_READY | 594000000 | | 158 | 5 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK | CLK_STATE_READY | 594000000 | | 158 | 6 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK | CLK_STATE_READY | 594000000 | | 158 | 7 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | CLK_STATE_READY | 600000000 | | 158 | 8 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0 | CLK_STATE_READY | 600000000 | | 158 | 9 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 148500000 | | 158 | 10 | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK | CLK_STATE_READY | 74250000 | | 158 | 11 | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 74250000 | | 158 | 12 | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK | CLK_STATE_READY | 297000000 | | 158 | 13 | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | CLK_STATE_READY | 300000000 | | 158 | 14 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK | CLK_STATE_READY | 148500000 | | 158 | 15 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 148500000 | | 158 | 16 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK | CLK_STATE_READY | 594000000 | | 158 | 17 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | CLK_STATE_READY | 600000000 | | 158 | 18 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK | CLK_STATE_READY | 594000000 | | 158 | 19 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK | CLK_STATE_READY | 594000000 | | 158 | 20 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK | CLK_STATE_READY | 594000000 | | 158 | 21 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK_DUP0 | CLK_STATE_READY | 594000000 | | 158 | 22 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | CLK_STATE_READY | 600000000 | | 158 | 23 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0 | CLK_STATE_READY | 600000000 | | 158 | 24 | DEV_DSS0_DSS_INST0_PARA_1_OUT_CLK | CLK_STATE_READY | 0 | | 158 | 25 | DEV_DSS0_DSS_INST0_PARA_3_OUT_CLK | CLK_STATE_READY | 0 | | 158 | 26 | DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK | CLK_STATE_READY | 0 | | 158 | 27 | DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK | CLK_STATE_READY | 0 | | 158 | 28 | DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK | CLK_STATE_READY | 0 | | 158 | 29 | DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK | CLK_STATE_READY | 0 | | 158 | 30 | DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK | CLK_STATE_READY | 0 | | 154 | 0 | DEV_DSS_DSI0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 154 | 1 | DEV_DSS_DSI0_SYS_CLK | CLK_STATE_READY | 250000000 | | 154 | 2 | DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK | CLK_STATE_READY | 0 | | 154 | 3 | DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK | CLK_STATE_READY | 20000000 | | 154 | 4 | DEV_DSS_DSI0_DPI_0_CLK | CLK_STATE_READY | 0 | | 154 | 5 | DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK | CLK_STATE_READY | 0 | | 155 | 0 | DEV_DSS_DSI1_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 155 | 1 | DEV_DSS_DSI1_SYS_CLK | CLK_STATE_READY | 250000000 | | 155 | 2 | DEV_DSS_DSI1_DPHY_0_RX_ESC_CLK | CLK_STATE_READY | 0 | | 155 | 3 | DEV_DSS_DSI1_DPHY_0_TX_ESC_CLK | CLK_STATE_READY | 20000000 | | 155 | 4 | DEV_DSS_DSI1_DPI_0_CLK | CLK_STATE_READY | 0 | | 155 | 5 | DEV_DSS_DSI1_PPI_0_TXBYTECLKHS_CL_CLK | CLK_STATE_READY | 0 | | 156 | 0 | DEV_DSS_EDP0_PHY_LN0_RXCLK | CLK_STATE_READY | 0 | | 156 | 1 | DEV_DSS_EDP0_PHY_LN2_TXCLK | CLK_STATE_READY | 0 | | 156 | 2 | DEV_DSS_EDP0_PHY_LN3_RXFCLK | CLK_STATE_READY | 0 | | 156 | 3 | DEV_DSS_EDP0_PHY_LN2_TXMCLK | CLK_STATE_READY | 0 | | 156 | 4 | DEV_DSS_EDP0_PHY_LN3_REFCLK | CLK_STATE_READY | 0 | | 156 | 6 | DEV_DSS_EDP0_DPI_2_2X_CLK | CLK_STATE_READY | 0 | | 156 | 7 | DEV_DSS_EDP0_PHY_LN0_TXCLK | CLK_STATE_READY | 0 | | 156 | 8 | DEV_DSS_EDP0_PHY_LN2_TXFCLK | CLK_STATE_READY | 0 | | 156 | 9 | DEV_DSS_EDP0_DPI_3_CLK | CLK_STATE_READY | 0 | | 156 | 10 | DEV_DSS_EDP0_PHY_LN1_RXCLK | CLK_STATE_READY | 0 | | 156 | 11 | DEV_DSS_EDP0_PHY_LN1_TXCLK | CLK_STATE_READY | 0 | | 156 | 12 | DEV_DSS_EDP0_PHY_LN1_RXFCLK | CLK_STATE_READY | 0 | | 156 | 13 | DEV_DSS_EDP0_DPI_5_CLK | CLK_STATE_READY | 0 | | 156 | 14 | DEV_DSS_EDP0_PHY_LN2_RXCLK | CLK_STATE_READY | 0 | | 156 | 16 | DEV_DSS_EDP0_PHY_LN1_TXMCLK | CLK_STATE_READY | 0 | | 156 | 18 | DEV_DSS_EDP0_DPI_2_CLK | CLK_STATE_READY | 0 | | 156 | 19 | DEV_DSS_EDP0_DPTX_MOD_CLK | CLK_STATE_READY | 125000000 | | 156 | 20 | DEV_DSS_EDP0_PHY_LN1_REFCLK | CLK_STATE_READY | 0 | | 156 | 21 | DEV_DSS_EDP0_PHY_LN1_TXFCLK | CLK_STATE_READY | 0 | | 156 | 22 | DEV_DSS_EDP0_PHY_LN0_RXFCLK | CLK_STATE_READY | 0 | | 156 | 24 | DEV_DSS_EDP0_PHY_LN3_TXMCLK | CLK_STATE_READY | 0 | | 156 | 25 | DEV_DSS_EDP0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 156 | 26 | DEV_DSS_EDP0_PHY_LN0_TXFCLK | CLK_STATE_READY | 0 | | 156 | 27 | DEV_DSS_EDP0_PHY_LN3_TXFCLK | CLK_STATE_READY | 0 | | 156 | 28 | DEV_DSS_EDP0_PHY_LN3_TXCLK | CLK_STATE_READY | 0 | | 156 | 29 | DEV_DSS_EDP0_PHY_LN2_REFCLK | CLK_STATE_READY | 0 | | 156 | 30 | DEV_DSS_EDP0_DPI_4_CLK | CLK_STATE_READY | 0 | | 156 | 31 | DEV_DSS_EDP0_PHY_LN0_TXMCLK | CLK_STATE_READY | 0 | | 156 | 33 | DEV_DSS_EDP0_PHY_LN0_REFCLK | CLK_STATE_READY | 0 | | 156 | 34 | DEV_DSS_EDP0_PHY_LN3_RXCLK | CLK_STATE_READY | 0 | | 156 | 35 | DEV_DSS_EDP0_AIF_I2S_CLK | CLK_STATE_READY | 0 | | 156 | 36 | DEV_DSS_EDP0_PHY_LN2_RXFCLK | CLK_STATE_READY | 0 | | 270 | 0 | DEV_MCU_NAVSS0_MODSS_VD2CLK | CLK_STATE_READY | 1000000000 | | 99 | 1 | DEV_MMCSD1_EMMCSDSS_XIN_CLK | CLK_STATE_READY | 200000000 | | 99 | 2 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 99 | 3 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | CLK_STATE_READY | 192000000 | | 99 | 4 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 99 | 5 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 99 | 6 | DEV_MMCSD1_EMMCSDSS_IO_CLK_O | CLK_STATE_READY | 0 | | 99 | 7 | DEV_MMCSD1_EMMCSDSS_IO_CLK_I | CLK_STATE_READY | 0 | | 99 | 8 | DEV_MMCSD1_EMMCSDSS_VBUS_CLK | CLK_STATE_READY | 250000000 | | 253 | 0 | DEV_NAVSS0_MODSS_VD2CLK | CLK_STATE_READY | 500000000 | | 254 | 0 | DEV_NAVSS0_MODSS_INTA_0_SYS_CLK | CLK_STATE_READY | 500000000 | | 255 | 0 | DEV_NAVSS0_MODSS_INTA_1_SYS_CLK | CLK_STATE_READY | 500000000 | | 365 | 25 | DEV_SERDES_10G0_IP1_LN2_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN2_TXCLK | CLK_STATE_READY | 0 | | 365 | 26 | DEV_SERDES_10G0_IP1_LN2_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN0_TXCLK | CLK_STATE_READY | 0 | | 365 | 33 | DEV_SERDES_10G0_IP1_LN3_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN3_TXCLK | CLK_STATE_READY | 0 | | 365 | 34 | DEV_SERDES_10G0_IP1_LN3_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN1_TXCLK | CLK_STATE_READY | 0 | 2. 1920x1080 | 158 | 0 | DEV_DSS0_DSS_FUNC_CLK | CLK_STATE_READY | 600000000 | | 158 | 1 | DEV_DSS0_DSS_INST0_DPI_0_IN_CLK | CLK_STATE_READY | 74250000 | | 158 | 2 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK | CLK_STATE_READY | 148500000 | | 158 | 3 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 148500000 | | 158 | 4 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0 | CLK_STATE_READY | 594000000 | | 158 | 5 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK | CLK_STATE_READY | 594000000 | | 158 | 6 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK | CLK_STATE_READY | 594000000 | | 158 | 7 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | CLK_STATE_READY | 600000000 | | 158 | 8 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0 | CLK_STATE_READY | 600000000 | | 158 | 9 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 148500000 | | 158 | 10 | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK | CLK_STATE_READY | 74250000 | | 158 | 11 | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 74250000 | | 158 | 12 | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK | CLK_STATE_READY | 297000000 | | 158 | 13 | DEV_DSS0_DSS_INST0_DPI_2_IN_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | CLK_STATE_READY | 300000000 | | 158 | 14 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK | CLK_STATE_READY | 148500000 | | 158 | 15 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 148500000 | | 158 | 16 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK | CLK_STATE_READY | 594000000 | | 158 | 17 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | CLK_STATE_READY | 600000000 | | 158 | 18 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK | CLK_STATE_READY | 594000000 | | 158 | 19 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK | CLK_STATE_READY | 594000000 | | 158 | 20 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK | CLK_STATE_READY | 594000000 | | 158 | 21 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK_DUP0 | CLK_STATE_READY | 594000000 | | 158 | 22 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | CLK_STATE_READY | 600000000 | | 158 | 23 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0_DUP0 | CLK_STATE_READY | 600000000 | | 158 | 24 | DEV_DSS0_DSS_INST0_PARA_1_OUT_CLK | CLK_STATE_READY | 0 | | 158 | 25 | DEV_DSS0_DSS_INST0_PARA_3_OUT_CLK | CLK_STATE_READY | 0 | | 158 | 26 | DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK | CLK_STATE_READY | 0 | | 158 | 27 | DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK | CLK_STATE_READY | 0 | | 158 | 28 | DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK | CLK_STATE_READY | 0 | | 158 | 29 | DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK | CLK_STATE_READY | 0 | | 158 | 30 | DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK | CLK_STATE_READY | 0 | | 154 | 0 | DEV_DSS_DSI0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 154 | 1 | DEV_DSS_DSI0_SYS_CLK | CLK_STATE_READY | 250000000 | | 154 | 2 | DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK | CLK_STATE_READY | 0 | | 154 | 3 | DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK | CLK_STATE_READY | 20000000 | | 154 | 4 | DEV_DSS_DSI0_DPI_0_CLK | CLK_STATE_READY | 0 | | 154 | 5 | DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK | CLK_STATE_READY | 0 | | 155 | 0 | DEV_DSS_DSI1_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 155 | 1 | DEV_DSS_DSI1_SYS_CLK | CLK_STATE_READY | 250000000 | | 155 | 2 | DEV_DSS_DSI1_DPHY_0_RX_ESC_CLK | CLK_STATE_READY | 0 | | 155 | 3 | DEV_DSS_DSI1_DPHY_0_TX_ESC_CLK | CLK_STATE_READY | 20000000 | | 155 | 4 | DEV_DSS_DSI1_DPI_0_CLK | CLK_STATE_READY | 0 | | 155 | 5 | DEV_DSS_DSI1_PPI_0_TXBYTECLKHS_CL_CLK | CLK_STATE_READY | 0 | | 156 | 0 | DEV_DSS_EDP0_PHY_LN0_RXCLK | CLK_STATE_READY | 0 | | 156 | 1 | DEV_DSS_EDP0_PHY_LN2_TXCLK | CLK_STATE_READY | 0 | | 156 | 2 | DEV_DSS_EDP0_PHY_LN3_RXFCLK | CLK_STATE_READY | 0 | | 156 | 3 | DEV_DSS_EDP0_PHY_LN2_TXMCLK | CLK_STATE_READY | 0 | | 156 | 4 | DEV_DSS_EDP0_PHY_LN3_REFCLK | CLK_STATE_READY | 0 | | 156 | 6 | DEV_DSS_EDP0_DPI_2_2X_CLK | CLK_STATE_READY | 0 | | 156 | 7 | DEV_DSS_EDP0_PHY_LN0_TXCLK | CLK_STATE_READY | 0 | | 156 | 8 | DEV_DSS_EDP0_PHY_LN2_TXFCLK | CLK_STATE_READY | 0 | | 156 | 9 | DEV_DSS_EDP0_DPI_3_CLK | CLK_STATE_READY | 0 | | 156 | 10 | DEV_DSS_EDP0_PHY_LN1_RXCLK | CLK_STATE_READY | 0 | | 156 | 11 | DEV_DSS_EDP0_PHY_LN1_TXCLK | CLK_STATE_READY | 0 | | 156 | 12 | DEV_DSS_EDP0_PHY_LN1_RXFCLK | CLK_STATE_READY | 0 | | 156 | 13 | DEV_DSS_EDP0_DPI_5_CLK | CLK_STATE_READY | 0 | | 156 | 14 | DEV_DSS_EDP0_PHY_LN2_RXCLK | CLK_STATE_READY | 0 | | 156 | 16 | DEV_DSS_EDP0_PHY_LN1_TXMCLK | CLK_STATE_READY | 0 | | 156 | 18 | DEV_DSS_EDP0_DPI_2_CLK | CLK_STATE_READY | 0 | | 156 | 19 | DEV_DSS_EDP0_DPTX_MOD_CLK | CLK_STATE_READY | 125000000 | | 156 | 20 | DEV_DSS_EDP0_PHY_LN1_REFCLK | CLK_STATE_READY | 0 | | 156 | 21 | DEV_DSS_EDP0_PHY_LN1_TXFCLK | CLK_STATE_READY | 0 | | 156 | 22 | DEV_DSS_EDP0_PHY_LN0_RXFCLK | CLK_STATE_READY | 0 | | 156 | 24 | DEV_DSS_EDP0_PHY_LN3_TXMCLK | CLK_STATE_READY | 0 | | 156 | 25 | DEV_DSS_EDP0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 156 | 26 | DEV_DSS_EDP0_PHY_LN0_TXFCLK | CLK_STATE_READY | 0 | | 156 | 27 | DEV_DSS_EDP0_PHY_LN3_TXFCLK | CLK_STATE_READY | 0 | | 156 | 28 | DEV_DSS_EDP0_PHY_LN3_TXCLK | CLK_STATE_READY | 0 | | 156 | 29 | DEV_DSS_EDP0_PHY_LN2_REFCLK | CLK_STATE_READY | 0 | | 156 | 30 | DEV_DSS_EDP0_DPI_4_CLK | CLK_STATE_READY | 0 | | 156 | 31 | DEV_DSS_EDP0_PHY_LN0_TXMCLK | CLK_STATE_READY | 0 | | 156 | 33 | DEV_DSS_EDP0_PHY_LN0_REFCLK | CLK_STATE_READY | 0 | | 156 | 34 | DEV_DSS_EDP0_PHY_LN3_RXCLK | CLK_STATE_READY | 0 | | 156 | 35 | DEV_DSS_EDP0_AIF_I2S_CLK | CLK_STATE_READY | 0 | | 156 | 36 | DEV_DSS_EDP0_PHY_LN2_RXFCLK | CLK_STATE_READY | 0 | | 270 | 0 | DEV_MCU_NAVSS0_MODSS_VD2CLK | CLK_STATE_READY | 1000000000 | | 99 | 1 | DEV_MMCSD1_EMMCSDSS_XIN_CLK | CLK_STATE_READY | 200000000 | | 99 | 2 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 99 | 3 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | CLK_STATE_READY | 192000000 | | 99 | 4 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 99 | 5 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 99 | 6 | DEV_MMCSD1_EMMCSDSS_IO_CLK_O | CLK_STATE_READY | 0 | | 99 | 7 | DEV_MMCSD1_EMMCSDSS_IO_CLK_I | CLK_STATE_READY | 0 | | 99 | 8 | DEV_MMCSD1_EMMCSDSS_VBUS_CLK | CLK_STATE_READY | 250000000 | | 253 | 0 | DEV_NAVSS0_MODSS_VD2CLK | CLK_STATE_READY | 500000000 | | 254 | 0 | DEV_NAVSS0_MODSS_INTA_0_SYS_CLK | CLK_STATE_READY | 500000000 | | 255 | 0 | DEV_NAVSS0_MODSS_INTA_1_SYS_CLK | CLK_STATE_READY | 500000000 | | 365 | 25 | DEV_SERDES_10G0_IP1_LN2_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN2_TXCLK | CLK_STATE_READY | 0 | | 365 | 26 | DEV_SERDES_10G0_IP1_LN2_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN0_TXCLK | CLK_STATE_READY | 0 | | 365 | 33 | DEV_SERDES_10G0_IP1_LN3_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN3_TXCLK | CLK_STATE_READY | 0 | | 365 | 34 | DEV_SERDES_10G0_IP1_LN3_TXCLK_PARENT_K3_DSS_EDP_MAIN_0_PHY_LN1_TXCLK | CLK_STATE_READY | 0 | however the set of the timing log is totally different 1. 2560x1440 [MCU2_0] 5.327269 s: APP: Configuring DSS for 2560x1440@30Hz (eDP) resolution... [MCU2_0] 5.327306 s: prm.timings.width = 2560 [MCU2_0] 5.327330 s: prm.timings.height = 1440 [MCU2_0] 5.327354 s: prm.timings.hFrontPorch = 48 [MCU2_0] 5.327378 s: prm.timings.hBackPorch = 80 [MCU2_0] 5.327401 s: prm.timings.hSyncLen = 32 [MCU2_0] 5.327424 s: prm.timings.vFrontPorch = 3 [MCU2_0] 5.327447 s: prm.timings.vBackPorch = 33 [MCU2_0] 5.327471 s: prm.timings.vSyncLen = 5 [MCU2_0] 5.327497 s: prm.timings.pixelClock = 241699200 [MCU2_0] 5.327515 s: DSS: Init ... !!! [MCU2_0] 5.327531 s: DSS: Display type is eDP !!! [MCU2_0] 5.327547 s: DSS: M2M Path is enabled !!! [MCU2_0] 5.327564 s: DSS: SoC init ... !!! tivxImagingLoadKernels done 15.543089 s: ISS: Enumerating sensors ... !!! [MCU2_0] 5.327579 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=0 [MCU2_0] 5.327718 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 5.327739 s: SCICLIENT: Sciclient_pmSetModuleState module=365 state=2 [MCU2_0] 5.327887 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 5.327906 s: SCICLIENT: Sciclient_pmSetModuleState module=156 state=2 [MCU2_0] 5.328036 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 5.328057 s: SCICLIENT: Sciclient_pmSetModuleState module=365 state=2 [MCU2_0] 5.328241 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 5.328264 s: SCICLIENT: Sciclient_pmSetModuleState module=156 state=2 [MCU2_0] 5.328431 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 5.328450 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=0 [MCU2_0] 5.328621 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 5.328641 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=158 clk=3 freq=241699200 [MCU2_0] 5.329574 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success [MCU2_0] 5.329598 s: SCICLIENT: Sciclient_pmModuleClkRequest module=158 clk=3 state=2 flag=2 [MCU2_0] 5.329790 s: SCICLIENT: Sciclient_pmModuleClkRequest success [MCU2_0] 5.329810 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=2 [MCU2_0] 5.330035 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 5.330057 s: DSS: SoC init ... Done !!! [MCU2_0] 5.330072 s: DSS: Board init ... !!! [MCU2_0] 5.330088 s: DSS: Turning on DP_PWR pin for eDP adapters ... !!! [MCU2_0] 5.875595 s: DSS: Turning on DP_PWR pin for eDP adapters ... Done!!! [MCU2_0] 5.875630 s: DSS: Board init ... Done !!! [MCU2_0] 5.875957 s: DP Link Rate set to 2.7Gbps x 2 lanes for J721S2 [MCU2_0] 5.954644 s: DSS: Init ... Done !!! 2. 1920x1080 [MCU2_0] 5.221171 s: FVID2: Init ... !!! [MCU2_0] 5.221220 s: FVID2: Init ... Done !!! [MCU2_0] 5.221243 s: SCICLIENT: Sciclient_pmSetModuleState module=219 state=2 [MCU2_0] 5.221325 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 5.221371 s: prm.timings.width = 1920 [MCU2_0] 5.221397 s: prm.timings.height = 1080 [MCU2_0] 5.221422 s: prm.timings.hFrontPorch = 88 [MCU2_0] 5.221445 s: prm.timings.hBackPorch = 148 [MCU2_0] 5.221468 s: prm.timings.hSyncLen = 44 [MCU2_0] 5.221491 s: prm.timings.vFrontPorch = 4 [MCU2_0] 5.221515 s: prm.timings.vBackPorch = 36 [MCU2_0] 5.221537 s: prm.timings.vSyncLen = 5 [MCU2_0] 5.221563 s: prm.timings.pixelClock = 148500000 [MCU2_0] 5.221582 s: DSS: Init ... !!! [MCU2_0] 5.221598 s: DSS: Display type is eDP !!! [MCU2_0] 5.221614 s: DSS: M2M Path is enabled !!! [MCU2_0] 5.221631 s: DSS: SoC init ... !!! [MCU2_0] 5.221646 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=0 tivxImagingLoadKernels done 46.293782 s: ISS: Enumerating sensors ... !!! [MCU2_0] 5.221715 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 5.221735 s: SCICLIENT: Sciclient_pmSetModuleState module=365 state=2 [MCU2_0] 5.221886 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 5.221905 s: SCICLIENT: Sciclient_pmSetModuleState module=156 state=2 [MCU2_0] 5.222032 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 5.222052 s: SCICLIENT: Sciclient_pmSetModuleState module=365 state=2 [MCU2_0] 5.222229 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 5.222253 s: SCICLIENT: Sciclient_pmSetModuleState module=156 state=2 [MCU2_0] 5.222418 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 5.222437 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=0 [MCU2_0] 5.222611 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 5.222631 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=158 clk=3 freq=148500000 [MCU2_0] 5.222821 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success [MCU2_0] 5.222842 s: SCICLIENT: Sciclient_pmModuleClkRequest module=158 clk=3 state=2 flag=2 [MCU2_0] 5.222970 s: SCICLIENT: Sciclient_pmModuleClkRequest success [MCU2_0] 5.222992 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=2 [MCU2_0] 5.223183 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_0] 5.223203 s: DSS: SoC init ... Done !!! [MCU2_0] 5.223219 s: DSS: Board init ... !!! [MCU2_0] 5.223238 s: DSS: Turning on DP_PWR pin for eDP adapters ... !!! [MCU2_0] 5.769228 s: DSS: Turning on DP_PWR pin for eDP adapters ... Done!!! [MCU2_0] 5.769262 s: DSS: Board init ... Done !!! [MCU2_0] 5.769584 s: DP Link Rate set to 2.7Gbps x 2 lanes for J721S2 [MCU2_0] 5.848276 s: DSS: Init ... Done !!!https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1619781/am623-am62x-sr1-0-hs-fs-deep-sleep-entry-ok-but-wake-always-cold-boot-gpio-rtc-wake-and-60s-timeout-behaviour/6378698Thu, 11 Jun 2026 05:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d6aba6ab-0516-4b0e-bf2a-8d7757b27717Vishakha NayakHi Anshu, In addition to the above messages (related to the TIFS logs capture query), we also instrumented the DM dm-stub (version-matched MCU+SDK 11.01.00.16) to dump the MAIN PSC registers at the disable_main_lpsc() timeout. At LPSC_A53_CLUSTER_0 (42): - PTSTAT = 0x08 → PD3 transition never completes (the timeout) - PDSTAT(3) = 0x317 → WAIT_ALL_SWRST_DIS (stuck before the switch/rail stages → not a rail/PMIC issue) - MDSTAT(42) = 0x11F0A → clock still running, resets de-asserted, EMURST set MDSTAT(42) read from U-Boot at idle (no debugger attached) = 0x11F03 — EMURST is asserted continuously, not just during suspend. The per-core LPSC (45) disables fine; only the cluster is stuck. Root cause: our JTAG pins incl. TRSTN are No-Connect (floating). A floating TRSTN keeps the debug TAP out of reset, so the debug subsystem stays active and holds EMURST on the A53 cluster, blocking it from reaching SwRstDisable. This matches SPRAD21 (TRSTN must be pulled low via 4.7k when JTAG is unused). The same SDK/TI-SCI flow works on the SK-EVM, which terminates JTAG correctly. Constraints: TRSTN (ball B10) is unroutable on the current board — under the BGA, no pad/via/test point — so no bench fix is possible. We are on HS-FS and are not converting to HS-SE at this stage, because we are still in the development stage. Questions: 1. Is there ANY HS-FS software/firmware way to stop the debug subsystem holding the cluster — e.g. a soft-TRST / way to hold the TAP in reset, a DEBUGSS or A53-cluster debug reset assertable from the DM or U-Boot, or clearing EDPRCR.CORENPDRQ per core before suspend? Or is a floating TRSTN only fixable in hardware on HS-FS? 2. For the next hardware board rev: will a 4.7k pull-down on TRSTN to GND (or a proper JTAG/EMU termination) clear the EMURST hold and let the cluster power down so Deep Sleep completes? We want to confirm it&#39;s the correct and sufficient fix before designing it in. Happy to share the full WKUP traces, the register dump, and our DM instrumentation patch. Thanks, Vishakhahttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1653939/am1808-schematics-evb/6378695Thu, 11 Jun 2026 05:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a4474acf-aafe-4734-9864-4d71d14c3052Shashank vaidyaHi, Thank you sreenivasa. Does it mean, no documents are available?https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1654385/tda4vh-q1-sfp-recommendationThu, 11 Jun 2026 05:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b8b217b5-6b3c-4f98-975a-df4b62c18464phytecBSCPart Number: TDA4VH-Q1 Hello Ti. We have implemented 2 SFP+ Sockets on our carrierboard and would like to know if you have a recommendation for moduls which are already supported or tested in some way. Funnily I found the same question in the forum, but wihout result, or the link is not working properly. Would this work? https://www.ti.com/lit/ug/snlu325/snlu325.pdf?ts=1781159872617&amp;ref_url=https%253A%252F%252Fstatics.teams.cdn.office.net%252F But here the question would be where to get it. Cheers, meTDA4VH-Q1Aerospace &amp; Defensehttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1649626/am62a3-tog_app_am62ax-sk_mcu-r5fss0-0_nortos_ti-arm-clang/6378643Thu, 11 Jun 2026 04:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:680642c7-f7f9-41f3-ae2f-534a23d23293Nihar PotturuHi Wang, Please find the TOG Freertos example below: e2e.ti.com/.../stog.zip Please update the abort handler similar to ECC example(Attaching example below) and rebuild nortos and freertos libs. void TEXT_HWI WEAK HwiP_user_data_abort_handler_c(DFSR dfsr, ADFSR adfsr, volatile uint32_t DFAR, volatile uint32_t LR,volatile uint32_t SPSR) { uint32_t *ptr=(uint32_t *)0xA0000000; if(*ptr==0xDEADBEAF) { *ptr=0; uint32_t zero=0; /* Clear DFSR (Data Fault Status Register): CP15, c5, c0, 0 */ __asm volatile (&quot;MCR p15, 0, %0, c5, c0, 0&quot; :: &quot;r&quot;(zero)); /* Clear ADFSR (Auxiliary DFSR): CP15, c5, c1, 0 */ __asm volatile (&quot;MCR p15, 0, %0, c5, c1, 0&quot; :: &quot;r&quot;(zero)); /* Clear DFAR (Data Fault Address Register): CP15, c6, c0, 0 */ __asm volatile (&quot;MCR p15, 0, %0, c6, c0, 0&quot; :: &quot;r&quot;(zero)); /* ISB to ensure register writes complete before returning */ __asm volatile (&quot;ISB&quot;); } else { volatile uint32_t loop = 1U; while(loop != 0U){ ; } } } Regards, Nihar Potturuhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1653961/am62a7-q1-am62a7-request-for-lcpd-46301-patch-details-for-gstreamer-v4l2videoenc-cma-memory-leak-on-sdk-10-0/6378626Thu, 11 Jun 2026 04:19:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c8804b0a-4fbf-4765-8d19-8ab22cf648e1Suren PorwarHi Anshi, Attaching a zip file that contains root filesystem, script for migrating 1.22 to 1.24 (which resolves the memory leak issue) and also a wic image if you want to validate it on our EVM. edgeai-image.zip Please be sure to download and test. The folders contained include the following : 1. root-filesystem. This is the tarball of the rootfs that you can run tar -xf on. this holds everything for new rootfs of course, but this is also where each new gstreamer file is as well. 2. script-to-change-gst-versions. Please note that this is a bash script generated by claude (necessary for the recursive dependenices and symlinks involved), which was invoked after finding the required changes. 3. validation - the python script to validate start/stop of gstreamer pipeline involving encoding every 2secs. 4. wic-image - the image that you can flash if desired. Hope this helps Best Regards Suren