https://e2e.ti.com/support/processors-group/processors/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1684379/am62l-linux-sdk-am62l-sdk-11-00-15-05-otp-keywriter-vs-keywriter-lite-support/6502091Mon, 05 Oct 2026 21:03:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:88aa84ea-ecc6-45d5-8caf-4c09f758ddb5Hong Guan64Hi Nilesh, please refer to the link on how to capture the TIFS trace https://software-dl.ti.com/tisci/esd/latest/4_trace/trace.html https://software-dl.ti.com/tisci/esd/latest/3_boardcfg/BOARDCFG.html#design-details-for-system-firmware-debug-console Best, -Honghttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1686783/am62l-am62l---recommended-provisioning-flow-keywriter-lite-vs-otp-keywriter-vs-keywriter-for-am62l-otp-lite-keywriter/6502083Mon, 05 Oct 2026 20:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f71b997e-df3e-43a0-a505-9cafee3c3c3cHong Guan641/. The new AM62L keywriter-full will be released in the near future. I&#39;ll share more details once I have it. - the key certificate blob is different comparing full vs lite, =&gt; two different TISCI APIs (refer to the two links) https://software-dl.ti.com/tisci/esd/latest/6_topic_user_guides/key_writer.html https://software-dl.ti.com/tisci/esd/latest/6_topic_user_guides/key_writer_lite.html - two different TIFS binary: one special TIFS binary only for keywriter-full (to be released) one regular TIFS binary for normal boot as well as keywriter-lite (available now) 2/. The special TIFS binary for keywriter-full runs only on HS-FS Best, -Honghttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1686758/am6442-graceful-shutdown-on-multiple-cores/6502031Mon, 05 Oct 2026 19:59:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0db5497b-4264-4454-ab14-845869efd8f2Nick SaulnierHello Martin, Side tangent: how to use remoteprocX First, please note that remoteprocX designations are NOT fixed on each boot. The first core that Linux is aware of becomes remoteproc0, the next one is remoteproc1, and so on. Because of random timings during boot, you will pretty regularly see the exact core association of remoteprocX changing from boot to boot. If you need to be specific about which core is getting turned on and off, then you would need to use something like /sys/class/remoteproc/remoteproc*/name to make sure you are interacting with the correct core. What is weird about your outputs Usually we see error -16 (EBUSY) if the non-Linux core never sends the ACK back to Linux. That&#39;s this part of the driver: ret = wait_for_completion_timeout(&amp;kproc-&gt;shutdown_complete, msecs_to_jiffies(5000)); if (ret == 0) { dev_err(kproc-&gt;dev, &quot;%s: timeout waiting for rproc completion event\n&quot;, __func__); return -EBUSY; } Since you didn&#39;t see that output, I assume that you ARE successfully sending the ACK back. It seems like readx_poll_timeout calls is_core_in_wfi until the function returns true or 2msec pass. If there aren&#39;t any more error outputs, we don&#39;t really have enough information to say for sure what is happening (e.g., did the is_core_in_wfi request fail? Did it time out after 2msec?) Next steps Are you comfortable modifying the Linux driver code and rebuilding the Linux kernel &amp; modules to run tests? I would be curious if you still saw the behavior if you increased the timeout value passed to readx_poll_timeout (e.g., to 100 msec). If the behavior went away, that could point to the non-Linux core just taking longer than Linux expects to get to WFI (or the device management core not updating the status of the WFI flag within that amount of time). You could also try adding some more useful error outputs to the driver to better see where the issue is coming from. Is this only seen with R5F cores? It could be useful to start noting which core is having the issue. I would be surprised if it mattered, but there is some power sequencing required by the hardware when bringing core0 and core1 of the same R5F subsystem up. Off the top of my head, not sure if that could matter here. Regards, Nickhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1687061/am3354-future-linux-sdk-support-and-update-frequency/6501994Mon, 05 Oct 2026 18:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f4d514ca-340b-4d0d-8394-bde33acdc995Praneeth BajjuriMichael V , Related Thread: AM3358: Support for SGX beyond kernel 6.12 For AM335x we plan to make a release in Nov 2026 with Latest LTS ( 6.18 kernel , Yocto Wrynose) and Uboot 2026.01 combination . We have already been making CICD based snapshot releases of the same baseline since 1Q already. Ref: https://software-dl.ti.com/cicd-report/linux/index.html?section=platform&amp;platform=am335x Same trend as last 5+ years ( One release a year based on active LTS Kernel and Yocto LTS) . Ref: https://www.ti.com/tool/download/PROCESSOR-SDK-LINUX-AM335X -- TI Strategy is always to release LTS based releases for these platforms (Including AM62) . For AM335x is in maintenance mode , whereas AM62 is still getting new features beyond LTS Migration . Hence you see a different cadence but atleast one latest LTS based release every year so far . -- Hope it clarifies. Regards Praneethhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1684693/tda4al-q1-dphy-rx-memory-mapped-registers-addresses/6501970Mon, 05 Oct 2026 18:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:74f1ec4a-a8eb-414b-aba9-bcbdd11e451bMark L.Hi Mohamed, I followed up through email. Regards, Markhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1674358/am6442-status-update-request-for-dp83869hm-bmcr-11-pwdn-investigation/6501929Mon, 05 Oct 2026 17:55:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2abe925b-7571-4d65-8ed6-15969b97ddf5Gerome CachoHi Michael, I do not have a TMDS64EVM readily available on me. However, I am looking at other options at the moment. As I am a PHY expert rather than TMDS expert, this may be best answered by TMDS team. Sincerely, Geromehttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1685292/tda4vh-q1-tda4vh-q1-lpddr4-configuration-inquiries-for-lt--ht-temperature-cycle-test-zq-mr18-mr19-sref/6501913Mon, 05 Oct 2026 17:48:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:dd8c9ea7-5e5c-4a31-a0be-2d3f1af63f18Kevin SHi, [quote userid=&quot;697238&quot; url=&quot;~/support/processors-group/processors/f/processors-forum/1685292/tda4vh-q1-tda4vh-q1-lpddr4-configuration-inquiries-for-lt--ht-temperature-cycle-test-zq-mr18-mr19-sref/6500992&quot;] Re-training Mechanism: Since MR18/MR19 are not used, how exactly does the TDA4x DDRSS perform this periodic DQS-DQ re-training?[/quote] The re-training occurs periodically based on a timer. At 4266 MT/s, the re-training should be occurring approximately once per 63 ms. [quote userid=&quot;697238&quot; url=&quot;~/support/processors-group/processors/f/processors-forum/1685292/tda4vh-q1-tda4vh-q1-lpddr4-configuration-inquiries-for-lt--ht-temperature-cycle-test-zq-mr18-mr19-sref/6500992&quot;] DRAM-side involvement: During this re-training process, does the SoC send any specific commands to the LPDDR4 memory, or is the compensation handled entirely within the SoC?[/quote] Yes, the DRAM is involved. The procedure should be similar to the write DQ to DQS training which occurs during initialization. [quote userid=&quot;697238&quot; url=&quot;~/support/processors-group/processors/f/processors-forum/1685292/tda4vh-q1-tda4vh-q1-lpddr4-configuration-inquiries-for-lt--ht-temperature-cycle-test-zq-mr18-mr19-sref/6500992&quot;] Disable Switch: Regarding your question, yes. To isolate variables during our specific temperature cycle test, we would like to know how to disable this periodic re-training feature from a hardware/register perspective.[/quote] It can be disabled by setting the re-train interval to 0x0. (i.e, set DDRSS_PI_71[15:0] = 0x0 for each DDRSS) However, I am not entirely clear on the end objective. The system will not pass temperature cycle tests without re-training enabled. Can you further clarify on what variables you are trying to isolate? Regards, Kevinhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1685352/j784s4xevm-multi-cam-not-streaming/6501888Mon, 05 Oct 2026 17:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b1dc101a-3b32-4049-9cf3-50563e405851DARSHAN SHi Gokul, we are using 11.2 psdk , gmsl serdes max96717 and max 96724 in tunnel mode configuration . The application prints &quot;ISS: Starting sensor [OX03N10] ... Done !!! &quot; and the interactive options are available but after that application is stuck and no stream on display . J784S4-ospas122@QNX8:/# /vision_apps/vx_app_multi_cam_default.out --cfg /vision_apps/app_multi_cam.cfg APP: Init QNX ... !!! appIpcInit: IPC: Init QNX ... !!! appIpcInit: IPC: Init ... Done !!! 417.158434 s: REMOTE_SERVICE: Init ... !!! 417.158527 s: REMOTE_SERVICE: Init ... Done !!! 417.160789 s: GTC Frequency = 200 MHz APP: Init ... Done !!! 417.160823 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 417.160841 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 417.160860 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 417.161047 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 417.161136 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 417.161225 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 417.161310 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 417.161334 s: VX_ZONE_INFO: [tivxInitLocal:202] Initialization Done !!! 417.161354 s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO 417.161763 s: ISS: Enumerating sensors ... !!! 417.161992 s: ISS: Enumerating sensors ... found 0 : OX03N10 1 sensor(s) found Supported sensor list: a : OX03N10 Select a sensor above or press &#39;0&#39; to autodetect the sensor [MCU2_0] 417.161886 s: OX03N10IssSensor_DeserializerInit returned status: -1 a Sensor selected : OX03N10 Querying OX03N10 430.272321 s: ISS: Querying sensor [OX03N10] ... !!! 430.272476 s: ISS: Querying sensor [OX03N10] ... Done !!! LDC Selection Yes(1)/No(0) Invalid selection . Try again LDC Selection Yes(1)/No(0) 0 Max number of cameras supported by sensor OX03N10 = 8 Please enter number of cameras to be enabled 2 433.828196 s: ISS: Initializing sensor [OX03N10], doing IM_SENSOR_CMD_PWRON ... !!! [MCU2_0] 433.828361 s: OX03N10IssSensor_PowerOn : chMask = 3 chId = 0x0 [MCU2_0] 433.828453 s: OX03N10Driver Version 0.10 [MCU2_0] 433.828689 s: OX03N10[configureI2cAccess] I2C0 current moduleState=1, resetState=0 [MCU2_0] 433.828789 s: OX03N10[configureI2cAccess] I2C0 powered on successfully [MCU2_0] 433.828920 s: OX03N10[configureI2cAccess] Current FWL: control=0x0, perm[0]=0x0, start=0x2000000, end=0x2000fff [MCU2_0] 433.829044 s: OX03N10[configureI2cAccess] Firewall configured successfully for I2C0 [MCU2_0] 433.829150 s: OX03N10[configureI2cAccess] After config FWL: control=0xa, perm[0]=0xd4ffff [MCU2_0] 433.829266 s: OX03N10Probing I2C bus 0 [MCU2_0] 433.829291 s: OX03N10 0 1 2 3 4 5 6 7 8 9 a b c d e f [MCU2_0] 433.829794 s: OX03N1000: -- -- -- -- -- -- -- -- -- -- -- -- -- [MCU2_0] 433.830415 s: OX03N1010: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- [MCU2_0] 433.831001 s: OX03N1020: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- [MCU2_0] 433.831577 s: OX03N1030: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- [MCU2_0] 433.832180 s: OX03N1040: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- [MCU2_0] 433.832767 s: OX03N1050: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- [MCU2_0] 433.833372 s: OX03N1060: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- [MCU2_0] 433.833684 s: OX03N1070: -- -- -- -- -- -- -- -- [MCU2_0] 433.888044 s: OX03N10 [MCU2_0] 433.888733 s: OX03N10Probing I2C bus 0 [MCU2_0] 433.888760 s: OX03N10 0 1 2 3 4 5 6 7 8 9 a b c d e f [MCU2_0] 433.889602 s: OX03N1000: -- -- -- -- -- -- -- -- -- -- -- -- -- [MCU2_0] 433.890609 s: OX03N1010: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- [MCU2_0] 433.891896 s: OX03N1020: 20 -- -- -- -- -- -- -- -- -- -- -- -- -- 2e -- [MCU2_0] 433.893177 s: OX03N1030: -- -- -- -- -- -- 36 -- -- -- 3a -- -- -- -- -- [MCU2_0] 433.894182 s: OX03N1040: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- [MCU2_0] 433.895449 s: OX03N1050: -- -- -- -- 54 -- -- -- -- -- -- -- 5c -- -- -- [MCU2_0] 433.896465 s: OX03N1060: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- [MCU2_0] 433.896998 s: OX03N1070: -- -- -- -- -- -- -- -- [MCU2_0] 433.897029 s: OX03N10Ox03N10_PowerOn : chId = 0x0 [MCU2_0] 433.897054 s: OX03N10IssSensor_PowerOn : chMask = 1 chId = 0x1 [MCU2_0] 433.897119 s: OX03N10Driver Version 0.10 [MCU2_0] 433.897143 s: OX03N10Probing I2C bus 0 [MCU2_0] 433.897163 s: OX03N10 0 1 2 3 4 5 6 7 8 9 a b c d e f [MCU2_0] 433.897994 s: OX03N1000: -- -- -- -- -- -- -- -- -- -- -- -- -- [MCU2_0] 433.899004 s: OX03N1010: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- [MCU2_0] 433.900270 s: OX03N1020: 20 -- -- -- -- -- -- -- -- -- -- -- -- -- 2e -- [MCU2_0] 433.901547 s: OX03N1030: -- -- -- -- -- -- 36 -- -- -- 3a -- -- -- -- -- [MCU2_0] 433.902547 s: OX03N1040: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- [MCU2_0] 433.903816 s: OX03N1050: -- -- -- -- 54 -- -- -- -- -- -- -- 5c -- -- -- [MCU2_0] 433.904860 s: OX03N1060: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- [MCU2_0] 433.905388 s: OX03N1070: -- -- -- -- -- -- -- -- [MCU2_0] 433.970043 s: OX03N10 [MCU2_0] 433.970704 s: OX03N10Probing I2C bus 0 [MCU2_0] 433.970729 s: OX03N10 0 1 2 3 4 5 6 7 8 9 a b c d e f [MCU2_0] 433.971552 s: OX03N1000: -- -- -- -- -- -- -- -- -- -- -- -- -- 434.042065 s: ISS: Initializing sensor [OX03N10], doing IM_SENSOR_CMD_CONFIG ... !!! [MCU2_0] 433.973864 s: OX03N1020: -- 21 -- -- -- -- -- -- -- -- -- -- -- -- 2e -- [MCU2_0] 433.975145 s: OX03N1030: -- -- -- -- -- -- 36 -- -- -- -- 3b -- -- -- -- [MCU2_0] 433.976171 s: OX03N1040: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- [MCU2_0] 433.977448 s: OX03N1050: -- -- -- -- 54 -- -- -- -- -- -- -- 5c -- -- -- [MCU2_0] 433.978470 s: OX03N1060: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- [MCU2_0] 433.979009 s: OX03N1070: -- -- -- -- -- -- -- -- [MCU2_0] 433.979042 s: OX03N10Ox03N10_PowerOn : chId = 0x1 442.624091 s: ISS: Initializing sensor [OX03N10] ... Done !!! 442.793454 s: ISS: Starting sensor [OX03N10] ... !!! [MCU2_0] 442.793611 s: OX03N10Warning : channel ID 0 already has a registered sensor handle [MCU2_0] 442.803859 s: OX03N10OX03N10_StreamOn: chId = 0x00 Lane configuration set to 2 Fmt : RAW16 442.813948 s: ISS: Starting sensor [OX03N10] ... Done !!! ========================= Demo : Camera Demo ========================= s: Save CSIx, VISS and LDC outputs p: Print performance statistics x: Exit [MCU2_0] 442.803914 s: OX03N10Warning : channel ID 1 already has a registered sensor handle [MCU2_0] 442.813857 s: OX03N10OX03N10_StreamOn: chId = 0x01 Lane configuration set to 2 Fmt : RAW16 Thanks, Darshanhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1641077/am6442-xdp-zero-copy-for-cpsw/6501868Mon, 05 Oct 2026 17:12:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9fccd7f0-baa7-46bc-819f-43fe066fa1cdRohit SinghHi Artur, As Daolin said in their previous message, they will be out of office until late next week. I was helping her run some tests last week for this issue so I will try to provide support while she is out. I ran the test on AM64x SDK 11.2 RT-Linux Yocto with no core pinning, no isolated CPUs, no SysMultiCore in the CODESYS config, and even after running network traffic on the non-XDP port while running the CODESYS application in parallel I was not able to recreate the unbalanced enable IRQ issue you were seeing. [quote userid=&quot;492655&quot; url=&quot;~/support/processors-group/processors/f/processors-forum/1641077/am6442-xdp-zero-copy-for-cpsw/6501206&quot;]I&#39;ve a am64x-evm board, I could run the tests on that board. [/quote] Running a test on the am64x-evm would be a good next step as it will help us isolate whether it is a hardware or software issue and give us more clarity on how to replicate the setup on our end. I can provide the exact SD Card wic image I used on my evm so that you can see if you still see the issue on your end. I&#39;m not sure if the forums will let me upload the file since its a little large, so if the below link doesn&#39;t work we can look into a good email that I can share the file with. am64x-rt-oct-2-codesys-xdp.wic.xz Best Regards, Rohithttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1686853/mspm0g3507-ccs-breakpoint/6501802Mon, 05 Oct 2026 16:19:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:059d2dbb-6d11-441b-bb93-181029555f6eDave PeterAnd then after some use it broke againhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1686320/tda4vh-q1-main-r5-peripheral-access/6501784Mon, 05 Oct 2026 16:04:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ac5ebdf8-a9de-4afe-b7a7-d9c127886f9cSuman AnnaHi Jim, [quote userid=&quot;346969&quot; url=&quot;~/support/processors-group/processors/f/processors-forum/1686320/tda4vh-q1-main-r5-peripheral-access/6501729&quot;]Any idea why GP does not need power up, but HSFS need?[/quote] The Timer power behavior is agnostic of SoC device type, should behave the same way between GP and HS-FS, unless your software is creating a distinction. regards Sumanhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1682340/tda4vm-unable-to-find-submitted-tda4vm-design-checklist-schematic-review-request-on-e2e/6501746Mon, 05 Oct 2026 15:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d22c9e4b-acd3-48e5-b598-0323422e8565Robert EschlerI am sorry you are having issues using E2E. I&#39;m unclear on the problem - as you are able to submit this E2E ticket without issue. I see you also submitted a TDA4VM Schematic review request +1year ago - but you never included the completed checklist and/or schematic. ( Link ) Are you looking for the checklist? Its available here: Link (Note the Link is to PDF instruction, the actual checklist XLS is linked in the PDF)https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1686320/tda4vh-q1-main-r5-peripheral-access/6501729Mon, 05 Oct 2026 15:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:15e1e474-0961-4815-86d5-8b02677986c9Jim ZhangAny idea why GP does not need power up, but HSFS need?https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1676465/tms320c6657-dsp-rom-bootloader-rbl-nand-bootloader-support-ecc/6501715Mon, 05 Oct 2026 15:20:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:91e7ce6d-9918-4cee-a409-772f2c87676ftom deakinsI dont think you or the expert are getting what the issue is. There is no sw running other than the rom bootloader (rbl) embedded in the device. The rbl is the only sw running and it cannot correct a bit error in the nand image as it reads it during direct NAND boot.https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1686320/tda4vh-q1-main-r5-peripheral-access/6501709Mon, 05 Oct 2026 15:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:eb3aee47-5992-42d0-93bb-2663a290f849Suman AnnaHi Jim, Jason, FWIW, I don&#39;t think Firewalls is the root-cause for your issues. Please ensure the peripheral is powered up before using it. regards Sumanhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1686320/tda4vh-q1-main-r5-peripheral-access/6501707Mon, 05 Oct 2026 15:16:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a05a4b46-ac7d-4f25-9084-879fceae7ce2Suman AnnaHi Jim, [quote userid=&quot;346969&quot; url=&quot;~/support/processors-group/processors/f/processors-forum/1686320/tda4vh-q1-main-r5-peripheral-access/6501693&quot;]Do you have example app for using TISCI_MSG_SET_FWL_REGION to reconfigure the firewall?[/quote] I have provided the reference for this earlier, the sciclient_fw_testapp is an example application dealing with Firewalls. [quote userid=&quot;35368&quot; url=&quot;~/support/processors-group/processors/f/processors-forum/1686320/tda4vh-q1-main-r5-peripheral-access/6498895&quot;]You can also look up the Sciclient unit test references in / /packages/ti/drv/sciclient/examples/sciclient_unit_testapp and sciclient_fw_testapp folders for reference Sciclient usage.[/quote] regards Sumanhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1686970/tda4vm-q1-how-to-generate-the-otp-file-using-keywriter-and-what-customer-has-to-provide-in-it/6501701Mon, 05 Oct 2026 15:07:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6e59849c-3239-4f4e-9af1-a4f4eb50e399Suman AnnaHi Harshil, [quote userid=&quot;686421&quot; url=&quot;~/support/processors-group/processors/f/processors-forum/1686970/tda4vm-q1-how-to-generate-the-otp-file-using-keywriter-and-what-customer-has-to-provide-in-it&quot;] I was refering the below link: https://software-dl.ti.com/tisci/esd/09_02_07/6_topic_user_guides/key_writer.html [/quote] This provides the generic details of the KeyWriter functionality within the TIFS firmware. Please see the 5.17. OTP KEYWRITER section of the PDK documentation, this details the KeyWriter application portion. [quote userid=&quot;686421&quot; url=&quot;~/support/processors-group/processors/f/processors-forum/1686970/tda4vm-q1-how-to-generate-the-otp-file-using-keywriter-and-what-customer-has-to-provide-in-it&quot;]I Would like to know how to generate the Keywriter for custom board and what customer has to provide in it.[/quote] You will need to port this application for your board. The primary adjustments needed are based on the PDN solution used by your board for providing the VPP_EFUSE (Voltage supply for eFuses). The KeyWriter certificate needs to be generated on your HSM Server. regards Sumanhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1686320/tda4vh-q1-main-r5-peripheral-access/6501693Mon, 05 Oct 2026 14:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6233a016-dfff-413b-be77-1859378a6d68Jim ZhangSuman: Thank you so much for the quick answer! Do you have example app for using TISCI_MSG_SET_FWL_REGION to reconfigure the firewall?https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1685887/am62a3-questions-about-gpmc-read-latency-and-multiple-address-phases-during-16-bit-write/6501687Mon, 05 Oct 2026 14:45:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:78b5030a-94bb-4942-ae6d-a1945d8c3497Anastas YordanovHi Conor-san, Thank you for performed measurements and updated inputs ! I will review and provide my feedback. Thank you, Best Regards Anastashttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1686320/tda4vh-q1-main-r5-peripheral-access/6501683Mon, 05 Oct 2026 14:43:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:382f40e2-0b0a-41a5-ab64-f4ec14dbbfc6Suman AnnaHi Jim, [quote userid=&quot;346969&quot; url=&quot;~/support/processors-group/processors/f/processors-forum/1686320/tda4vh-q1-main-r5-peripheral-access/6501670&quot;]The table from J784S4_Appendix_Public_20250628.xlsx (you pasted above) does not provide the firewall owner info for the timer, and the TISI website does not have the info either.[/quote] The Excel document provides only the h/w details on Firewall Ids for various peripherals. The latter showcases all the Firewalls that are configured by TIFS firmware on boot. It does not configure Firewalls for Timer or CAN peripherals, so there are no entries for any of Timer or CAN peripherals. This means they are not owned by any s/w component. [quote userid=&quot;346969&quot; url=&quot;~/support/processors-group/processors/f/processors-forum/1686320/tda4vh-q1-main-r5-peripheral-access/6501670&quot;]We are using TI HSFS soc, not GP soc. Is the ownership same for HSFS soc and GP soc?[/quote] Yes, the Firewall concepts are the same across GP, HS-FS or HS-SE devices. Please see the Firewall FAQ for a list of common questions on Firewalls. regards Suman