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Use of ecap0 ,ecap1 interface for pulse input on AM335x.

Intellectual 620 points

Replies: 17

Views: 4066

Hi

Has any body worked on using the ECAP API to develop a pulse input count functionality. 

I have to used  GPIO pin  and  used rising edge interrupts for counting pulse. But these have limitation. I need to count a *** of 20 to 20kHz . 

AM335x PWM driver doesn't support capture input  functionality. but found a  ecap_api.c  here  

  1. brief ECAP APIs.
  2. *
  3. * This file contains the device abstraction layer APIs for ECAP
  4. */

 and a good APIS which can work for you to get functionality from ecap module on AM335x theoritically. Btu the issue is how to provide the base address to these API's. 

Need help on this.

Thanks & Regards,

Uday Rajeshirke.

17 Replies

  • Is your question Android-related? Android is supported on a dedicated forum: https://e2e.ti.com/support/embedded/android/f/509

     

    Best Regards
    Biser
  • In reply to Biser Gatchev-XID:

    Hi biser,
    My question is not about android related.
    I am using TI SDK 7.00.00.00 with our custom board having am335x . I need help on writing driver for ecap interface to count the pulses throufh the isr.
    I have gone through this post.
    e2e.ti.com/.../1056108
    Understood what needs to be done . But need some help on how can I hook in to driver to add this functionality.
    Thanks & Regards,
    Uday Rajehsirke.
  • In reply to Uday Rajeshirke.:

    OK, I notified the Linux team.

     

    Best Regards
    Biser
  • In reply to Biser Gatchev-XID:

    Hi,
    waiting for reply.

    Thanks & Regards,
  • In reply to Uday Rajeshirke.:

    Hi Uday,

    Is this issue still pending?

    First of all you should configure your kernel appropriately, so that it initializes the ecap: clocks, pins, etc... You should create appropriate dts nodes & add the ecap & PWMSS in the kernel configuration (menucaonfig or through the defconfig file directly). Once you've done that your kernel should map the ecap_pwmss to /proc/interrupts, /proc/iomem, etc ... And the module will be accessible from user space.
    Working with those fs entries narrows down to using files in your userspce driver.

    As I see the ecap.c source you refer to is a user space driver that sets different functionalities of the ecap module. You need to create the appropriate header files: hw_pwmss.h, ecap.h, hw_types.h, hw_ecap.h which hold the definitions of the ECAP, PWMSS, PRCM and ohter used registers ( i couldn't find them in the link you provided, so I assume you'll have to create them yourself); you should define the base addresses from the device TRM.
    You should also define the HWREG() & HWREGH() macros for reading/writing to the registers, you can refer to the implementation of devmem2 for reference: free-electrons.com/.../devmem2.c (focus on remapping the base address to the virtual kernel address space).

    Then you can create a main() function that calls the apis from ecap.c to do the needed ecap module settings and implement the functionality described in the e2e post you refer. You should cross compile your user space driver and copy the binary to the filesystem on your board.

    Hope this helps.
    Best Regards,
    Yordan

     


     Please make sure you read the forum guidelines first.

  • In reply to Yordan Kovachev:

    Hi Yordan,
    Thanks for reply.
    I have configured a kernel for ecap driver compilation. I have modified a driver to enable ecap feature. Sysfs interface also done to enable ecap- capture mode. .
    But we are facing following problem.
    1) IRQ as per technical reference manual for the ECAP- CAP4 is 31 , 47 for ECAP0 ,ECAP1 interface respectively. But when we requesting IRS with this number it is not working a all. Means When we enable the ecap -capture mode it is getting enable but interrupts are not getting genereted when pulse input is provided.
    If we request IRS 47 ,63 interrupt is getting generated but it doesnt get stop even if pulse input is stopped. interrupt keeps on happening . We are counting the pulses in interrupt and doing nothing. After some time kernel gets panic and board hangs.

    @ Biser need your help in configuring the correct IRQ , disabling the interrupt sequence.
    Need urgent help on this. As it is pending for a long time.

    Thanking you in anticipation.

    Uday R.
  • In reply to Uday Rajeshirke.:

    Hi Uday,

    You should aim for IRQs 31 & 47, which correspond to ECAP0 & ECAP1. Not sure why IRQ63 is generated when using ECAP0 & ECAP1, as it is dedicated to GPIOINT3B (GPIO 3). Can you share your DTS file? I need the pinmux settings & modules configurations?

    In order to configure the correct IRQ, you need to ensure that INTC_ILR_31[bit0] = 0x0 & INTC_ILR_47[bit0]=0x0, but this should be the default configuration. However, could you please check the settings of those two registers? Also can you look into the values of ECEINT, ECFLG, ECCLR & ECFRC to ensure that interrupts are enabled on IP level?

    Best Regards,
    Yordan

     


     Please make sure you read the forum guidelines first.

  • In reply to Yordan Kovachev:

    Hi Yordan,
    Following are my device tree entry details related to ecap and the values I can read through sysfs. I have added these functionality for sysfs to return the register values.
    Please let me know if you want complete dtsi file.

    evice tree entries in dtsi:
    epwmss0: epwmss@48300000 {
    status = "okay";
    ecap0: ecap@48300100 {
    compatible = "ti,am33xx-ecap";
    #pwm-cells = <3>;
    reg = <0x48300100 0x80>;
    interrupts = <31>;
    interrupt-names = "ecap0";
    ti,hwmods = "ecap0";
    status = "okay";
    pinctrl-names = "default", "sleep";
    pinctrl-0 = <&ecap0_pins_default>;
    pinctrl-1 = <&ecap0_pins_sleep>;
    };
    };

    epwmss1: epwmss@48302000 {
    status = "okay";
    ecap1: ecap@48302100 {
    compatible = "ti,am33xx-ecap";
    #pwm-cells = <3>;
    reg = <0x48302100 0x80>;
    interrupts = <47>;
    interrupt-names = "ecap1";
    ti,hwmods = "ecap1";
    status = "okay";
    pinctrl-names = "default", "sleep";

    pinctrl-0 = <&ecap1_pins_default>;
    pinctrl-1 = <&ecap1_pins_sleep>;
    };
    };


    Console logs:
    Configuring through sysfs

    root@am335x-evm:~# echo 0 > /sys/class/pwm/pwmchip0/export
    root@am335x-evm:~# echo 1 > /sys/class/pwm/pwmchip0/pwm0/enable
    [ 26.145684] .....1
    [ 26.147855] .....ECAP_ECCLR = 1
    [ 26.151148] .....ECCTL2 = 6
    [ 26.154073] .....ECAP_ECEINT = 0
    root@am335x-evm:~# echo 1 > /sys/class/pwm/pwmchip0/pwm0/period
    [ 30.445467] .....2
    [ 30.447622] .....ECCTL2 = 86
    [ 30.450643] .....ECCTL1 = 155
    [ 30.453752] .....prescaler = 0 is set
    [ 30.457375] .....ECAP_ECEINT = 10
    [ 30.460859] .....ECCTL2 = 96
    [ 30.463879] .....ECAP_ECCLR = 0
    root@am335x-evm:~# echo 0 > /sys/class/pwm/pwmchip0/pwm0/enable
    [ 37.435364] .....nothing


    Pulse signal verification:
    When no pulse input is fed,
    root@am335x-evm:~# echo inversed > /sys/class/pwm/pwmchip0/pwm0/polarity
    [ 51.375673] .....3
    [ 51.377796] .....ECAP_ECFLG = 2
    [ 51.381090] .....cap1 = 0
    [ 51.383832] .....cap2 = 0
    [ 51.386621] .....cap3 = 0
    [ 51.389368] .....cap4 = 0

    When pulse input is fed
    root@am335x-evm:~# echo inversed > /sys/class/pwm/pwmchip0/pwm0/polarity
    [ 56.045556] .....3
    [ 56.047683] .....ECAP_ECFLG = 1f
    [ 56.051071] .....cap1 = 0
    [ 56.053816] .....cap2 = b747
    [ 56.056873] .....cap3 = 5343
    [ 56.059892] .....cap4 = ef1e
    root@am335x-evm:~# echo inversed > /sys/class/pwm/pwmchip0/pwm0/polarity
    [ 56.045556] .....3
    [ 56.047683] .....ECAP_ECFLG = 1f
    [ 56.051071] .....cap1 = 0
    [ 56.053816] .....cap2 = b747
    [ 56.056873] .....cap3 = 5343
    [ 56.059892] .....cap4 = ef1e
    root@am335x-evm:~# echo inversed > /sys/class/pwm/pwmchip0/pwm0/polarity
    [ 57.485409] .....3
    [ 57.487529] .....ECAP_ECFLG = 1f
    [ 57.490914] .....cap1 = 8af1
    [ 57.493935] .....cap2 = b747
    [ 57.496985] .....cap3 = 5343
    [ 57.500007] .....cap4 = ef1e


    Thanks & Regards,
    Uday Rajeshirke.
  • In reply to Uday Rajeshirke.:

    Hi,

    I see that ECAP_ECEINT = 10, which shows that interrupt event4 is enabled. From Table 6-2. Timer and eCAP Event Capture you can see that this is UART3 -> UART3INT.

    Can you verify that you don't use uart3, this may be the reason you keep getting interrupts on the UART3INT pin even though you've stopped the input pulses.
    Can you try adding interrupt-parent = <&used_irq_parent> to your ecap dts nodes, and see if the behavior of your setup will change?
    Also please attach the full DTS & DTSI files you use.

    Best Regards,
    Yordan

     


     Please make sure you read the forum guidelines first.

  • In reply to Yordan Kovachev:

    Hi ,

    We are using a uart3. Following is the dtsi file .

    /*
     * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
     *
     * This program is free software; you can redistribute it and/or modify
     * it under the terms of the GNU General Public License version 2 as
     * published by the Free Software Foundation.
     */

    / {
        model = "AM335x-EVM";
        compatible = "ti,am335x-bone", "ti,am33xx";

        cpus {
            cpu@0 {
                //cpu0-supply = <&dcdc2_reg>;
            };
        };

        memory {
            device_type = "memory";
            reg = <0x80000000 0x10000000>; /* 256 MB */
        };
            
        am33xx_pinmux: pinmux@44e10800 {
            pinctrl-names = "default";
            pinctrl-0 = <&clkout1_pin &keys_default>;

            /* Configuring GPIOs for pullup during startup of board  */
            keys_default: keys_default {
            pinctrl-single,pins = <
                    0x114 (PIN_INPUT_PULLUP | MUX_MODE7)    /* DIG_MPU_IP_2 */
                    0x118 (PIN_INPUT_PULLUP | MUX_MODE7)    /* DIG_MPU_IP_1 */
                    0x2C (PIN_INPUT_PULLUP | MUX_MODE7)        /*MPU_IGN_IP*/
                    0x144 (PIN_INPUT_PULLUP | MUX_MODE7)    /* MPU_KEY_IN_IP */
                    0x124 (PIN_INPUT_PULLUP | MUX_MODE7)    /*MPU_PANIC_IP*/
                    0x28 (PIN_INPUT_PULLUP | MUX_MODE7)    /*MPU_ACC_IP*/
                    0x198 (PIN_INPUT_PULLUP | MUX_MODE7)    /*IO_EXP2_INT*/
                    0x1A8 (PIN_INPUT_PULLUP | MUX_MODE7)    /*IO_EXP1_INT*/
                    0x24 (PIN_INPUT_PULLUP | MUX_MODE7)    /*ACC_INT1*/
                    0x58 (PIN_INPUT_PULLUP | MUX_MODE7)    /*ACC_INT2*/
                    0x20 (PIN_INPUT_PULLUP | MUX_MODE7)    /*CAN0_INH*/
                    0x80 (PIN_INPUT_PULLUP | MUX_MODE7)    /*TEMP_ALERT*/
                    0x38 (PIN_INPUT_PULLUP | MUX_MODE7)    /*GSM_STATUS*/
                    0x3C (PIN_INPUT_PULLUP | MUX_MODE7)    /*BATT_CHARGE*/
                    0x30 (PIN_INPUT_PULLUP | MUX_MODE7)    /*BATT_FAULT*/
                    0xc0 (PIN_OUTPUT | MUX_MODE7 )               /* (U1) lcd_data8.lcd_data8 */
                    0x194 (PIN_OUTPUT | MUX_MODE7 )         /* (B13) MPU_BAT_MON_EN */
                    0x200 ( PIN_INPUT | MUX_MODE7 )         /* (C5) EXT_WAKEUP.EXT_WAKEUP */
                    // 0x164  ( PIN_INPUT_PULLUP | MUX_MODE7 ) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
                    // 0x160 ( PIN_INPUT_PULLUP | MUX_MODE7 ) /* (C15) spi0_cs1.eCAP1_in_PWM1_out */
                    0xE4 (PIN_INPUT_PULLUP | MUX_MODE7)      /* LCD_HSYNC.gpio2_23, INPUT | MODE7 SIM DETECT*/
                    0x1b4 (PIN_INPUT_PULLUP | MUX_MODE7)    /* MPU_AUD_ON_OFF_IP */
                    >;
            };

            i2c0_pins: pinmux_i2c0_pins {
                pinctrl-single,pins = <
                    0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
                    0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
                >;
            };

            i2c1_pins: pinmux_i2c1_pins {
                pinctrl-single,pins = <
                    0x158 (PIN_INPUT_PULLUP | MUX_MODE2)    /* i2c1_sda.i2c1_sda */
                    0x15c (PIN_INPUT_PULLUP | MUX_MODE2)    /* i2c1_scl.i2c1_scl */
                >;
            };
        
            i2c2_pins: pinmux_i2c2_pins {
                pinctrl-single,pins = <
                    0x154 (PIN_INPUT_PULLUP | MUX_MODE2)    /* i2c2_sda.i2c2_sda */
                    0x150 (PIN_INPUT_PULLUP | MUX_MODE2)    /* i2c2_scl.i2c2_scl */
                >;
            };
                    
            /* UART pins */
        
            uart0_pins: pinmux_uart0_pins {
                pinctrl-single,pins = <
                    0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
                    0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
                >;
            };

            uart1_pins: pinmux_uart1_pins {
                pinctrl-single,pins = <
                    0x178 (PIN_INPUT | MUX_MODE0)            /* uart1_ctsn.uart1_ctsn */
                    0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart1_rtsn.uart1_rtsn */
                    0x180 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart1_rxd.uart1_rxd */
                    0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
                >;
            };

            uart2_pins: pinmux_uart2_pins {
                pinctrl-single,pins = <
                    0x12c (PIN_INPUT_PULLUP | MUX_MODE1)    /* uart2_rxd.uart2_rxd */
                    0x130 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* uart2_txd.uart2_txd */
                >;
            };

            uart3_pins: pinmux_uart3_pins {
                pinctrl-single,pins = <
                    0x134 (PIN_INPUT_PULLUP | MUX_MODE1)    /* mii1_rxd3.uart3_rxd */
                    0x138 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_rxd2.uart3_txd */
                >;
            };    

            uart5_pins: pinmux_uart5_pins {
                pinctrl-single,pins = <
                    0x148 (PIN_INPUT_PULLUP | MUX_MODE2)    /* uart5_rxd_mux3 */
                    0x14c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* uart5_txd_mux3 */
                >;
            };

            dcan0_pins: pinmux_dcan0_pins {
                pinctrl-single,pins = <
                    0x11c (PIN_OUTPUT_PULLUP | MUX_MODE1) /* dcan0_tx_mux0, (IDIS | OFF | MODE1 ) */
                    0x120 (PIN_INPUT_PULLUP | MUX_MODE1) /* dcan0_rx_mux0, (IEN | PD | MODE1 ) */
                >;
            };

            dcan1_pins: pinmux_dcan1_pins {
                pinctrl-single,pins = <
                    0x168 (PIN_OUTPUT_PULLUP | MUX_MODE2) /* dcan1_tx_mux0, (IDIS | OFF | MODE2 ) */
                    0x16c (PIN_INPUT_PULLUP | MUX_MODE2) /* dcan1_rx_mux0, (IEN | OFF | MODE2 ) */
                >;
            };
                            
            clkout1_pin: pinmux_clkout1_pin {
                pinctrl-single,pins = <
                    0x1b0 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* xdma_event_intr0.clkout1 */
                    // 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* xdma_event_intr1.clkout2 */
                >;
            };

            mmc1_pins_default: pinmux_mmc1_pins {
                pinctrl-single,pins = <
                    0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_dat3.mmc0_dat3 */
                    0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_dat2.mmc0_dat2 */
                    0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_dat1.mmc0_dat1 */
                    0x0FC (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_dat0.mmc0_dat0 */
                    0x100 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_clk.mmc0_clk */
                    0x104 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_cmd.mmc0_cmd */
                >;
            };

            mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
                pinctrl-single,pins = <
                    0x0F0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x0F4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x0F8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x0FC (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                >;
            };

            nandflash_pins_default: nandflash_pins_default {
                pinctrl-single,pins = <
                    0x0 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad0.gpmc_ad0 */
                    0x4 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad1.gpmc_ad1 */
                    0x8 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad2.gpmc_ad2 */
                    0xc (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad3.gpmc_ad3 */
                    0x10 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad4.gpmc_ad4 */
                    0x14 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad5.gpmc_ad5 */
                    0x18 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad6.gpmc_ad6 */
                    0x1c (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_ad7.gpmc_ad7 */
                    0x70 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_wait0.gpmc_wait0 */
                    0x74 (PIN_INPUT_PULLUP | MUX_MODE0)    /* gpmc_wpn.gpmc_wpn */
                    0x7c (PIN_OUTPUT | MUX_MODE0)        /* gpmc_csn0.gpmc_csn0  */
                    0x90 (PIN_OUTPUT | MUX_MODE0)        /* gpmc_advn_ale.gpmc_advn_ale */
                    0x94 (PIN_OUTPUT | MUX_MODE0)        /* gpmc_oen_ren.gpmc_oen_ren */
                    0x98 (PIN_OUTPUT | MUX_MODE0)        /* gpmc_wen.gpmc_wen */
                    0x9c (PIN_OUTPUT | MUX_MODE0)        /* gpmc_be0n_cle.gpmc_be0n_cle */
                >;
            };

            nandflash_pins_sleep: nandflash_pins_sleep {
                pinctrl-single,pins = <
                    0x0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0xc (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                >;
            };

            /* Abishek : added for ecap Support */
            ecap0_pins_default: ecap0_pins {
                pinctrl-single,pins = <
                    0x164 ( PIN_INPUT | MUX_MODE0 ) /* (C18) eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
                >;
            };

            ecap0_pins_sleep: ecap0_pins_sleep {
                pinctrl-single,pins = <
                    0x164  ( PIN_INPUT | MUX_MODE7 ) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
                >;
            };

            ecap1_pins_default: ecap1_pins {
                pinctrl-single,pins = <
                    0x160 ( PIN_INPUT | MUX_MODE2 ) /* (C15) spi0_cs1.eCAP1_in_PWM1_out */
                >;
            };

            ecap1_pins_sleep: ecap1_pins_sleep {
                pinctrl-single,pins = <
                    0x160  ( PIN_INPUT | MUX_MODE7 ) /* (C15) spi0_cs1.eCAP1_in_PWM1_out */
                >;
            };

            mcasp0_pins: mcasp0_pins {
                pinctrl-single,pins = <
                    0x60 (PIN_INPUT_PULLDOWN | MUX_MODE6)
                    0x64 (PIN_INPUT_PULLDOWN | MUX_MODE6)
                    0x68 (PIN_OUTPUT_PULLDOWN | MUX_MODE6)
                    0x6C (PIN_INPUT_PULLDOWN | MUX_MODE6)
                >;
            };

            mcasp0_sleep_pins: mcasp0_sleep_pins {
                pinctrl-single,pins = <
                    0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
                    0x6C (PIN_INPUT_PULLDOWN | MUX_MODE7)
                >;
            };

            
            /* Harsha : added for Wi-Fi Support */
            /* wl12xx/wl18xx card on mmc2 */
            mmc2_pins: pinmux_mmc2_pins {
                pinctrl-single,pins = <
                    0x44 (PIN_INPUT_PULLUP | MUX_MODE3)    /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
                    0x48 (PIN_INPUT_PULLUP | MUX_MODE3)    /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
                    0x4C (PIN_INPUT_PULLUP | MUX_MODE3)    /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
                    0x78 (PIN_INPUT_PULLUP | MUX_MODE3)    /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
                    0x88 (PIN_INPUT_PULLUP | MUX_MODE3)    /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
                    0x8C (PIN_INPUT_PULLUP | MUX_MODE3)    /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
                >;
            };

            mmc2_pins_sleep: pinmux_mmc2_pins_sleep {
                pinctrl-single,pins = <
                    0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.mmc1_clk */
                    0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.mmc1_cmd */
                    0x4C (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.mmc1_dat0 */
                    0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.mmc1_dat1 */
                    0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.mmc1_dat2 */
                    0x8C (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.mmc1_dat3 */
                >;
            };        

            /* wl12xx/wl18xx card enable/irq GPIOs. */
            wlan_pins: pinmux_wlan_pins {
                pinctrl-single,pins = <
                    0x10C (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gmii1_crs.gpio3_1 used for wi-fi EN */
                    0x110 (PIN_INPUT_PULLUP | MUX_MODE7)  /* MII1_RX_ER.gpio3_2 used for wi-fi IRQ */                
                >;
            };        
            
            /* wl12xx/wl18xx card enable/irq GPIOs. */
            wlan_pins_sleep: pinmux_wlan_pins_sleep {
                pinctrl-single,pins = <
                    0x10C (PIN_OUTPUT_PULLUP | MUX_MODE7)    /*gmii1_crs.gpio3_1 used for wi-fi EN*/
                    0x110 (PIN_INPUT_PULLUP | MUX_MODE7)    /* MII1_RX_ER.gpio3_2 used for wi-fi IRQ */
                >;
            };
            
        };

        ocp {

            musb: usb@47400000 {
                status = "okay";

                control@44e10000 {
                    status = "okay";
                };

                usb-phy@47401300 {
                    status = "okay";
                };

                usb-phy@47401b00 {
                    status = "okay";
                };

                usb@47401000 {
                    status = "okay";
                    dr_mode = "otg"; /* Harsha added on 4-12-14 for checking host mode */                
                };

                usb@47401800 {
                    status = "okay";
                    dr_mode = "host";
                };

                dma-controller@07402000  {
                    status = "okay";
                };
                
            };
            
            i2c0: i2c@44e0b000 {
                pinctrl-names = "default";
                pinctrl-0 = <&i2c0_pins>;
                status = "okay";
                clock-frequency = <400000>;
            };

            i2c1: i2c@4802a000 {
                pinctrl-names = "default";
                pinctrl-0 = <&i2c1_pins>;
                status = "okay";
                clock-frequency = <100000>;
                #if 0              
                wake-sequence = /bits/ 8 <
                0x02 0x21 0x06 0xEF /* Make pin as out put WL_EN PIN*/
                0x02 0x21 0x02 0x10 /* Enable the WL_EN pin to high */
                >;

                sleep-sequence = /bits/ 2 <
                0x02 0x21 0x06 0xEF /* Make pin as out put WL_EN PIN*/
                0x02 0x21 0x02 0x10 /* Enable the WL_EN pin to high */
                >;
                #endif            
                  
                tlv320aic3106: tlv320aic3106@1b {
                    compatible = "ti,tlv320aic3106";
                    reg = <0x1b>;
                    gpio-reset = <&gpio0 8 0>; /* GPIO_1 AUDIO_CODEC_RST  */
                    status = "okay";
                };

            };

             i2c2: i2c@4819c000 {
                pinctrl-names = "default";
                pinctrl-0 = <&i2c2_pins>;
                status = "okay";
                clock-frequency = <400000>;
            };
            
            /* UARTS */        
            uart0: serial@44e09000 {
                pinctrl-names = "default";
                pinctrl-0 = <&uart0_pins>;

                status = "okay";
            };

            uart1: serial@48022000 {
                pinctrl-names = "default";
                pinctrl-0 = <&uart1_pins>;

                status = "okay";
            };

            
            uart2: serial@48024000 {
                pinctrl-names = "default";
                pinctrl-0 = <&uart2_pins>;

                status = "okay";
            };

            uart3: serial@481a6000 {
                pinctrl-names = "default";
                pinctrl-0 = <&uart3_pins>;

                status = "okay";
            };

            uart5: serial@481aa000 {
                pinctrl-names = "default";
                pinctrl-0 = <&uart5_pins>;

                status = "okay";
            };

            dcan0: d_can@481cc000 {
                status = "okay";
                pinctrl-names = "default";
                pinctrl-0 = <&dcan0_pins>;
            };
                        
            dcan1: d_can@481d0000 {
                status = "okay";
                pinctrl-names = "default";
                pinctrl-0 = <&dcan1_pins>;
            };    
            
            /* Abishek : added for ecap Support */
            epwmss0: epwmss@48300000 {
            status = "okay";
            ecap0: ecap@48300100 {
                compatible = "ti,am33xx-ecap";
                #pwm-cells = <3>;
                reg = <0x48300100 0x80>;
                interrupts = <31>;
                interrupt-names = "ecap0";
                ti,hwmods = "ecap0";
                status = "okay";
                pinctrl-names = "default", "sleep";
                pinctrl-0 = <&ecap0_pins_default>;
                pinctrl-1 = <&ecap0_pins_sleep>;
                };
            };

            epwmss1: epwmss@48302000 {
            status = "okay";
            ecap1: ecap@48302100 {
                compatible = "ti,am33xx-ecap";
                #pwm-cells = <3>;
                reg = <0x48302100 0x80>;
                interrupts = <47>;
                interrupt-names = "ecap1";
                ti,hwmods = "ecap1";
                status = "okay";
                pinctrl-names = "default", "sleep";

                pinctrl-0 = <&ecap1_pins_default>;
                pinctrl-1 = <&ecap1_pins_sleep>;
                };
            };
            
            //200000000 - NAND Size
            gpmc: gpmc@50000000 {
                status = "okay";
                pinctrl-names = "default", "sleep";
                pinctrl-0 = <&nandflash_pins_default>;
                pinctrl-1 = <&nandflash_pins_sleep>;
                ranges = <0 0 0x08000000 0x10000000>;    /* CS0: NAND */
                nand@0,0 {
                    reg = <0 0 0>; /* CS0, offset 0 */
                    nand-bus-width = <8>;
                    gpmc,device-width = <1>;
                    gpmc,sync-clk-ps = <0>;
                    gpmc,cs-on-ns = <0>;
                    gpmc,cs-rd-off-ns = <44>;
                    gpmc,cs-wr-off-ns = <44>;
                    gpmc,adv-on-ns = <6>;
                    gpmc,adv-rd-off-ns = <34>;
                    gpmc,adv-wr-off-ns = <44>;
                    gpmc,we-on-ns = <0>;
                    gpmc,we-off-ns = <40>;
                    gpmc,oe-on-ns = <0>;
                    gpmc,oe-off-ns = <54>;
                    gpmc,access-ns = <64>;
                    gpmc,rd-cycle-ns = <82>;
                    gpmc,wr-cycle-ns = <82>;
                    gpmc,wait-on-read = "true";
                    gpmc,wait-on-write = "true";
                    gpmc,bus-turnaround-ns = <0>;
                    gpmc,cycle2cycle-delay-ns = <0>;
                    gpmc,clk-activation-ns = <0>;
                    gpmc,wait-monitoring-ns = <0>;
                    gpmc,wr-access-ns = <40>;
                    gpmc,wr-data-mux-bus-ns = <0>;
                    ti,nand-ecc-opt= "bch8";
                    ti,elm-id = <&elm>;
                    /* MTD partition table */
                            /* All SPL-* partitions are sized to minimal length
                     * which can be independently programmable. For
                     * NAND flash this is equal to size of erase-block */
                    #address-cells = <1>;
                    #size-cells = <1>;
                    partition@0 {
                        label = "NAND.SPL";
                        reg = <0x00000000 0x000020000>;
                    };
                    partition@1 {
                        label = "NAND.SPL.backup1";
                        reg = <0x00020000 0x00020000>;
                    };
                    partition@2 {
                        label = "NAND.SPL.backup2";
                        reg = <0x00040000 0x00020000>;
                    };
                    partition@3 {
                        label = "NAND.SPL.backup3";
                        reg = <0x00060000 0x00020000>;
                    };
                    partition@4 {
                        label = "NAND.u-boot-spl-os";
                        reg = <0x00080000 0x00040000>;
                    };
                    partition@5 {
                        label = "NAND.u-boot";
                        reg = <0x000C0000 0x00100000>;
                    };
                    partition@6 {
                        label = "NAND.u-boot-env";
                        reg = <0x001C0000 0x00020000>;
                    };
                    partition@7 {
                        label = "NAND.u-boot-env.backup1";
                        reg = <0x001E0000 0x00020000>;
                    };
                    partition@8 {
                        label = "NAND.kernel";
                        reg = <0x00200000 0x00800000>;
                    };
                    partition@9 {
                        label = "NAND.file-system";
                        reg = <0x00A00000 0x0F600000>;
                    };
                    partition@10 {
                        label = "NAND.file-system2";
                        reg = <0x10000000 0x30000000>;
                    };    
                };
            };    

            sound {
                    compatible = "ti,da830-evm-audio";
                    ti,model = "AM335x-EVM";
                    ti,audio-codec = <&tlv320aic3106>;
                    ti,mcasp-controller = <&mcasp0>;
                    ti,codec-clock-rate = <24000000>;
                    ti,audio-routing =
                        "Headphone Jack",       "HPLOUT",
                        "Headphone Jack",       "HPROUT";
                        #if 0
                        "LINE1L",               "Line In",
                        "LINE1R",               "Line In";                
                        #endif
            };            
        };



                        
        wlan_en_reg: fixedregulator@2 {
            compatible = "regulator-fixed";
            regulator-name = "wlan-en-regulator";                             
             regulator-min-microvolt = <1800000>;
             regulator-max-microvolt = <1800000>;
            /* WLAN_EN GPIO for this board - Bank3, pin1 */
            gpio = <&gpio3 1 0>;

            /* WLAN card specific delay */
            startup-delay-us = <70000>;
            enable-active-high;
        };

    #if 0    
    /* Ref. from file linux3.12/include/linux/wl12xx.h */
    /* Reference clock values */
    enum {
        WL12XX_REFCLOCK_19    = 0, /* 19.2 MHz */
        WL12XX_REFCLOCK_26    = 1, /* 26 MHz */
        WL12XX_REFCLOCK_38    = 2, /* 38.4 MHz */
        WL12XX_REFCLOCK_52    = 3, /* 52 MHz */
        WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
        WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
    };
    #endif    

        wlcore {
            compatible = "wlcore";
            gpio = <98>; /* Bank3, pin2 GPIO for Wi-Fi_IRQ */

            /*
             * TODO: use edge irqs for suspend/resume.
             * in newer kerenls, we seem to miss interrupts when
             * working with edge irqs, so revert back to level irqs.
             */
            /* platform-quirks = <1>; */

            /* if a 12xx card is there, configure the clock to
               WL12XX_REFCLOCK_38_XTAL */
            board-ref-clock = <4>;    
        };    


        vmmcsd_fixed: fixedregulator@0 {
            compatible = "regulator-fixed";
            regulator-name = "vmmcsd_fixed";
            regulator-min-microvolt = <3300000>;
            regulator-max-microvolt = <3300000>;
        };
    };

    &mcasp0 {
            pinctrl-names = "default", "sleep";
            pinctrl-0 = <&mcasp0_pins>;
            pinctrl-1 = <&mcasp0_sleep_pins>;

            status = "okay";

            op-mode = <0>;          /* MCASP_IIS_MODE */
            tdm-slots = <2>;
            /* 16 serializer */
            serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
                1 2 0 0
            >;
            tx-num-evt = <32>;
            rx-num-evt = <32>;
    };

    &mmc3 {
        /*these are on the crossbar and are outlined in the
        xbar-event-map element */
        dmas = <&edma 12
        &edma 13>;
        dma-names = "tx", "rx";
        status = "okay";
        vmmc-supply = <&wlan_en_reg>;
        bus-width = <4>;
        pinctrl-names = "default";
        pinctrl-0 = < &mmc2_pins &wlan_pins >;
        pinctrl-1 = < &mmc2_pins_sleep &wlan_pins_sleep >;
        ti,non-removable;
        ti,needs-special-hs-handling;
        cap-power-off-card;
        keep-power-in-suspend;
    };

    &edma {
        ti,edma-xbar-event-map = <1 12
        2 13>;
    };

    Thanks & Regards,

    Uday  Rajeshirke.

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