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Part Number: SITARA-DDR-CONFIG-TOOL
Dear TI Team,
we're using the EMIF configuration tool (AM65x/DRA80xM EMIF Tool Spreadsheet (ZIP 326 KB) 12 Oct 2018) to configure DDR controller settings for our custom AM6548 board.
So far we've noticed three (four) issues:
We've managed to work around the first issue (after figuring out what's going wrong) by switching to a dot as the decimal separator in our Excel settings.
We believe we can ignore the second issue for now, since the third issue means that C/A parity is disabled anyway. Is that correct?
Our current issue is that our DDR settings "work" for when using them via the GEL file (not thoroughly tested) and as part of our SBL (at least a brief automated RAM test succeeds), but fails when using them as part of U-Boot (based on ti-u-boot-2018.01). So far we've noticed that the U-Boot DDR initialization fails during the call to read_dqs_training() since the QSGERR (DQS gate training error) bit gets set.
We're still in the process of verifying all of the timing settings, but your colleagues suggested to inform you about issues with the EMIF tool early on. It would also be nice to know if there are any further (known) issues with the EMIF tool.
Our setup uses a single 16 bit DDR4 memory chip (MT40A256M16).
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
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In reply to JJD:
thanks for the newer version of the EMIF tool.
Unfortunately with the newer EMIF tool our results are actually worse.
We manually copied all our timings to the newer spreadsheet, since the .txt files that you can export are apparently incompatible. With the GEL file generated from these settings the GEL files fail, too, with errors in all of the training steps. There are quite a few differences in the GEL files generated by the EMIF tool v1.1 and v1.5, but we narrowed it down to the register values for PHY_DCR (bit UBG set) and PHY_ACIOCR3 (field BGOEMODE from 0x0->0x2). If we used the values for these registers generated with the tool v1.5 we get the training failures, if we use the values that were previously set with 1.1 (ACIOCR3 wasn't set at all) the training works.
We played around with the EMIF tool and noticed that switching "Total number of banks" between 16 and 8 changes exactly these two registers. Unfortunately the documentation doesn't really tell us what these mean. Can you tell us what the changes to PHY_ACIOCR3 and PHY_DCR mean? Is there a bug in the EMIF tool, or are we missing something?
We're also not really sure abut the right address mapping for our DDR4 memory:
We're using a single x16 chip with Column[9:0], Row[14:0], BA[1:0] and BG
With tool V1.1, the address mapping suggested by the tool after configuring width, column and row counts didn't really make sense, since it configured Row15 even though we set it to 15 rows total.
With tool V1.1 after manually changing the mapping to what we "thought" was right we had aliasing at offset 0x800: R[14:0], BG, BA[1:0], C[9:2]
With tool V1.1 we had a working GEL file with no aliasing after using the following mapping: R[14:0], BG, BA[1:0], C[8:2]
With tool V1.5, the mapping suggested by the tool (for total banks = 8) is what I'd expect: R[14:0], BG, BA[1:0], C[9:2], but we had the aliasing (after manually fixing PHY_ACIOCR3 and PHY_DCR)
With tool V1.5, the mapping that worked with V1.1 also worked, i.e. R[14:0], BG, BA[1:0], C[8:2]
The new tool V1.5 writes several additional registers that weren't set with V1.1. Can you tell us what the functional changes are from V1.1 to V1.5? For example the GEL produced by V1.5 writes the register DDRPHY_DX0GTR0 to 0x00020002 (from the reset default of 0x00020000). This sounds like something that could affect our original problem of DQS gate training failing within U-Boot, but the documentation just says "4-0 DGSL R/W 0h DQS Gating System Latency".
The documentation for the DDRSS registers in general is a bit chaotic, for example in terms of line breaks within the register field descriptions for fields like ADDRMAP_COL_B11, which makes it hard to tell which of the cases described in the description maps to which condition. The documentation also seems to copy too much from the (Synopsys(?)) IP core documentation, e.g. the documentation for DDRCTL_MSTR.DATA_BUS_WIDTH says
"Note that half bus width mode is only supported when the SDRAMbus width is a multiple of 16, and quarter bus width mode is onlysupported when the SDRAM bus width is a multiple of 32 and theconfiguration parameter MEMC_QBUS_SUPPORT is set."
I doubt that MEMC_QBUS_SUPPORT is a configuration parameter in the sense of the AM654x's programming capabilities, but rather something that had to be configured when synthesizing the DDRSS for the AM65x.
-> Is the EMIF Tool supposed to be useable for a AM65x with a single x16 chip and the geometry described above?
Regarding my issue about decimal separators:
The EMIF tool seems to operate correctly after switching my Excel from , to ., but the .txt files exported by tool use , again. If you want to import the tool settings you need to search&replace the .txt file and changes , back to .
In reply to Dominic Rath:
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