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Part Number: 66AK2G12
I am using "66AK2G12 "device . As two device evaluation boards are available on TI platform by Mistral solutions.
There is a difference in DDR3 termination section of board interfacing with SoC. In first board capacitors terminated with "DGND"
While on other board DDR3 termination section capacitor terminated with "1.35V " net name as (VDDS_DDR_K2G).
Please someone elaborate what is difference in both techniques or which one is better.?
Schematic cutout of both are Attached below.
Sorry for the late reply. Let me check that and I will update the thread.
Best Regards, Yordan
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The termination scheme on the K2GICE board matches that termination used in the JEDEC standard for DDR3L Unbuffered DIMMs. That should be the termination scheme used in your design.
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