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TMS320C6748: Unknown noise in signal processing when using L1 cache and MATH_LIB.

Prodigy 110 points

Replies: 5

Views: 147

Part Number: TMS320C6748

Environment

 - Board : TMS320C6748

 - CCS8.3.1

 - compiler version : 8.3.4

 - Used library : DSP_LIB, MATH_LIB

 - L1_CACHE_ENABLED

 - All the data stored in the DDR2

From McASP example code, I experiment a signal processing algorithm.

The experiment condition is:

Sampling rate : 16000Hz

Buffer size : 512

With L1_CACHE_ENABLED and log10sp_v, there is noise of the speaker output, which is not when I comment out L1_CACHE_ENABLED and log10sp_v.

Of course I verified the clean output value in the code before It is transferred to speaker output.

Therefore, It seems that the noise is occurred in the codec.

In this case, how could I remove the noise without disabling L1 cache and MATH_LIB?

Any advice or information request is welcome.

Thank you

  • Hello,

    Have you tried performing cache operations on the buffers to see if the noise goes away?

    Which software package are you using? Depending on which one, I can point you to the cache API to use. 

    Regards,
    Sahin


  • Can you please indicate what does the L1_CACHE_ENABLED Macro do in your code. does it simply enable L1D and L1P Cache ? Is L2 configured as SRAM or part SRAM and part cache. Is the EDMA moving any code from DDR to DSP internal memory for processing? Please also clarify doesn`t noise go away with cache enabled but without use of log10sp_v. I am trying to eliminate variables and want to understand why you suspect MATHLIB function is playing a role here.

    Also indicate if the Buffer is aligned to cache line boundary and as per the requirements of MATHLIB functions.

    Regards,

    Rahul

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  • In reply to Sahin Okur:

    I refer to CACHE_dspLib_fft_dspL138 example that using the CACHE rCSL.

    The example code includes some functions that control the cache.

    I used setup_DDR2_cache() and enable_L1() functions.

    when I comment out these functions, the noise goes away.

    So I thought the cache may occurs problem.

  • In reply to Rahul Prabhu:

    I using the rCSL cache functions, so following codes are rCSL cache example codes.

    static void setup_DDR2_cache (void)
    {
    	// Set SDRAM (MAR 192 - 223) as cacheable
    	for(counter = 192; counter < 224; counter++)
    		CSL_FINST(cacheRegs->MAR[counter], CACHE_MAR_PC, CACHEABLE);
    }/* setup_SDRAM_cache */
    
    /*---------------------------------------------------------------------------*/
    
    static void enable_L1 (void)
    {
    	// Set L1P size to 32K
    	CSL_FINST(cacheRegs->L1PCFG, CACHE_L1PCFG_MODE, 32K);
    	stall = cacheRegs->L1PCFG;
    	
    	// Set L1D size to 32K
    	CSL_FINST(cacheRegs->L1DCFG, CACHE_L1DCFG_MODE, 32K);
    	stall = cacheRegs->L1DCFG;
    }/* enable_L1 */
    
    /*---------------------------------------------------------------------------*/
    
    static void enable_L2 (void)
    {
    	// Set L2 size to 256K
    	CSL_FINST(cacheRegs->L2CFG, CACHE_L2CFG_MODE, 256K);
    	stall = cacheRegs->L2CFG;
    }/* enable_L2 */

    As you can see, there is a code that enabling the L2 cache, but If using that code it does not work correctly.

    So I used static void setup_DDR2_cache () and static void enable_L1() functions.

    And actually I didn't use any code about L2 cache, I don't know how it works in my project.

    Following codes are my linker command.

    MEMORY
    {
        DSPL2ROM     o = 0x00700000  l = 0x00100000   /* 1MB L2 Internal ROM */
        DSPL2RAM     o = 0x00800000  l = 0x00040000   /* 256kB L2 Internal RAM */
        DSPL1PRAM    o = 0x00E00000  l = 0x00008000   /* 32kB L1 Internal Program RAM */
        DSPL1DRAM    o = 0x00F00000  l = 0x00008000   /* 32kB L1 Internal Data RAM */
        SHDSPL2ROM   o = 0x11700000  l = 0x00100000   /* 1MB L2 Shared Internal ROM */
        SHDSPL2RAM   o = 0x11800000  l = 0x00040000   /* 256kB L2 Shared Internal RAM */
        SHDSPL1PRAM  o = 0x11E00000  l = 0x00008000   /* 32kB L1 Shared Internal Program RAM */
        SHDSPL1DRAM  o = 0x11F00000  l = 0x00008000   /* 32kB L1 Shared Internal Data RAM */
        EMIFACS0     o = 0x40000000  l = 0x20000000   /* 512MB SDRAM Data (CS0) */
        EMIFACS2     o = 0x60000000  l = 0x02000000   /* 32MB Async Data (CS2) */
        EMIFACS3     o = 0x62000000  l = 0x02000000   /* 32MB Async Data (CS3) */
        EMIFACS4     o = 0x64000000  l = 0x02000000   /* 32MB Async Data (CS4) */
        EMIFACS5     o = 0x66000000  l = 0x02000000   /* 32MB Async Data (CS5) */
        SHRAM        o = 0x80000000  l = 0x00020000   /* 128kB Shared RAM */
        DDR2         o = 0xC0000000  l = 0x20000000   /* 512MB DDR2 Data */
    }
    
    SECTIONS                                       
    {                                              
        .text          >  DDR2
        .stack         >  DDR2
        .bss           >  DDR2
        .cio           >  DDR2
        .const         >  DDR2
        .data          >  DDR2
        .switch        >  DDR2
        .sysmem        >  DDR2
        .far           >  DDR2
        .args          >  DDR2
        .ppinfo        >  DDR2
        .ppdata        >  DDR2
      
        /* COFF sections */
        .pinit         >  DDR2
        .cinit         >  DDR2
      
        /* EABI sections */
        .binit         >  DDR2
        .init_array    >  DDR2
        .neardata      >  DDR2
        .fardata       >  DDR2
        .rodata        >  DDR2
        .c6xabi.exidx  >  DDR2
        .c6xabi.extab  >  DDR2
    }

    As you can see, all of my codes and data are stored in DDR2 memory.

    So I think there is codes that moved from DDR2 to DSP internal memory.

    I'll explain following "noise go away with cache enabled but without use of log10sp_v"

    There are two scenarios.

    First.

    If I comment out setup_DDR2_cache () and enable_L1() functions, it works correctly.

    In that case I still use MATHLIB like a log10sp_v.

    Second.

    If I comment out MATHLIB codes, also it works correctly.

    In that case I still use cache functions.

    So I suspect cache functions ans MATHLIB both.

    I don't know what exactly occurring problem, so please give me some advice.

    Thank you.

  • In reply to gibeom kim:

    Discussion has been continued in the thread below so I am closing this one. 

    https://e2e.ti.com/support/processors/f/791/t/838599


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