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Max Bandwidth of EMIF 16 for TMS320C6657 to FPGA?

joe lindula
Mastermind 6850 points
Other Parts Discussed in Thread: TMS320C6655

Hi, I would like to use the EMIF 16 Peripheral to link to an Altera FPGA. I want to know the maximum bandwidth for the EMIF 16 link.  I'm looking over the data sheet for the TMS320C6655/57 on page 201 and 202 and Table 7-69 and the equation for Tc(CEL) (WS+WST+WH+TA+4)*E-3 is for the minimum time and the max time is (WS+WST+WH_TA+4)*E+3. The trouble I"m having is I don't know where to look to find the values for WS, WST, WH, TA and E. Does anyone know where I can find these values?

Thanks,

joe

  • 0
    TI__Expert 6815 points

    Joe,

    WS, WST and WH represent the setup, strobe and hold values for the EMIF16 write cycle. RS, RST and RH are the same for the read cycle. TA refers to the turnaround time.

    These are the timing values that need to be programmed in the Async config register for the chip select in question. Please refer to the EMIF16 users guide (sprugz3a) for more details.

    For back-to-back reads or writes to the same chip select, TA does not come into the picture. With this in mind, your read or write cycle is simply the sum of the read or write setup, strobe and hold times. Keep in mind that the minimum  you can program for each of these 3 is one EMIF16 clock cycle (EMIF16 clock = CPU/6).

    So at 1GHz, your theoretical max BW with a 16-bit interface is 16/(setup+strobe+hold) = 16/(1+1+1)EMIF clock cycles = 888.88 Mb/s. Changing the individual timing values will obviously give you different theoretical maximums.

    Hope this answers your question.

  • 0
    Mastermind 6850 points

    Hello, I found some useful informaiton on the post titled, "Use EMIF16 as interface for FPGA". But I'm still looking for the values.

     

    joe

  • 0 in reply to joe lindula
    TI__Expert 6815 points

    Joe,

    What values are you looking for in particular?

  • 0 in reply to Aditya
    Mastermind 6850 points

    Thanks Aditya! You've answered my question perfectly.

  • 0 in reply to Aditya
    Mastermind 6850 points

    Aditya,

     

    Hello, in your calculation above does that BW apply to all DSP's that run at 1Ghz and have an EMIF16 IF? I'm looking over the Keystone Architecture External Memory IF (EMIF16) document and to me it seems that all EMIF16 IF would have the same timing I/O. I've looked at other posts and some have 11  CPU/6 clock cycles per read and write and others say the can get 3 clock cycles per read/write. Can you help me straighten things out?

    thanks,

    joe

  • 0 in reply to Aditya
    Mastermind 6850 points

    Aditya,

     

    Hi, I'm looking over the data sheet for the TMS320C6655/57 on page 201 it describes the EMIF16 Peripheral. I'm looking over the equation for EMIF read cycle time when we= 0: (RS + RST + RH + 3) * E -3. This is No. 3 in Table 7-69. Can you please tell me the value of E? Is that programmable?

    Thank you very much for helping me understand this IF,

    joe

  • 0 in reply to joe lindula
    TI__Expert 6815 points

    Hi Joe,

    I believe the EMIF16 on all Keystone devices is clocked at CPU/6. I cannot comment on other devices (you will have to be specific) but I'm sure you will be able to find out from their data manuals or forums.

  • 0 in reply to joe lindula
    TI__Expert 6815 points

    Joe,

    Please see the other thread for this answer: RE: Use EMIF16 as interface for FPGA