Can display YCbCr 16bit (embedded sync) at dm36x ?

I can't open your URL ( http://e2e.ti.com/support/dsp/davinci_digital_media_processors/int-dm3x/f/102/p/32510/181080.aspx)

But we did check signal by logic analyzer.

the result is ok. YCbCr 16 Bit embedded sync is out. (SAV/EAV is right)

It's my mistake.

conclusion is  that DM36X can display YCbCr 16 bit embedded sync or separate sync by digital output

thank you

Hi Sungil Kim,

As I saw, you may already success in setting for 16bit Embedded Sync and Non Embedded sync Digital out. Can you share some thing to me for the correct configuration?

thanks

I can't  exactly what is problem so i upload some code (this code is work now)

I hope it help you

enum HDMI_MODE_E {
HDMI_480I,
HDMI_576I,
HDMI_480P,
HDMI_576P,
HDMI_720P_60,
HDMI_720P_50,
HDMI_1080I_30,
HDMI_1080I_25,
HDMI_1080P_60,
HDMI_1080P_50,
};

static void davinci_enc_set_digital_ycbcr16(struct vid_enc_mode_info *mode_info,int hdmi_mode)
{
enableDigitalOutput(1);

/* set VPSS clock */

dispc_reg_out(VENC_DCLKCTL, 0);
dispc_reg_out(VENC_DCLKPTN0, 0);
dispc_reg_out(VENC_CLKCTL, 0x10);
davinci_cfg_reg(DM365_VOUT_COUTL_EN, PINMUX_RESV);
davinci_cfg_reg(DM365_VOUT_COUTH_EN, PINMUX_RESV);

{
int i=1;
int data;
data = davinci_readl(0x01C40000 + 0x4*i);
data = data & (~(1<<17));
data = data & (~(1<<22));
davinci_writel(data,(0x01C40000 + 0x4*i));
}

//davinci_cfg_reg(DM365_VOUT_HVSYNC, PINMUX_RESV);

dispc_reg_out(VENC_VIDCTL,0);
/* Set VIDCTL to select VCLKE = 1,
VCLKZ =0, SYDIR = 0 (set o/p), DOMD = 0 */
dispc_reg_merge(VENC_VIDCTL, 1 << VENC_VIDCTL_VCLKE_SHIFT,
VENC_VIDCTL_VCLKE);
dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_VCLKZ_SHIFT,
VENC_VIDCTL_VCLKZ);
dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_SYDIR_SHIFT,
VENC_VIDCTL_SYDIR);
dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_YCDIR_SHIFT,
VENC_VIDCTL_YCDIR);

dispc_reg_merge(VENC_DCLKCTL,
1 << VENC_DCLKCTL_DCKEC_SHIFT, VENC_DCLKCTL_DCKEC);

dispc_reg_out(VENC_DCLKPTN0, 0x1);
davinci_enc_set_display_timing(mode_info);

switch(hdmi_mode)
{
case HDMI_480P:
printk(KERN_INFO "HDMI 480P\n");
davinci_writel(0x28, SYS_VPSS_CLKCTL);
dispc_reg_out(VENC_VMOD, 0x0503);
dispc_reg_out(VENC_XHINTVL,0);
break;

case HDMI_576P:
printk(KERN_INFO "HDMI 576P\n");
davinci_writel(0x28, SYS_VPSS_CLKCTL);
dispc_reg_out(VENC_VMOD, 0x0543);
dispc_reg_out(VENC_XHINTVL,0);
break;

case HDMI_720P_60:
printk(KERN_INFO "HDMI 720P 60Hz\n");
davinci_writel(0x28, SYS_VPSS_CLKCTL);
dispc_reg_out(VENC_VMOD, 0x05c3);
dispc_reg_out(VENC_XHINTVL,0);
break;

case HDMI_720P_50:
printk(KERN_INFO "HDMI 720P 50Hz\n");
davinci_writel(0x28, SYS_VPSS_CLKCTL);
davinci_writel(0x28, SYS_VPSS_CLKCTL);
dispc_reg_out(VENC_VMOD, 0x05c3);
dispc_reg_out(VENC_XHINTVL,330);
break;

case HDMI_1080I_30:
printk(KERN_INFO "HDMI 1080P30\n");
davinci_writel(0x28, SYS_VPSS_CLKCTL);
dispc_reg_out(VENC_VMOD, 0x0183);
dispc_reg_out(VENC_XHINTVL,0);
break;

case HDMI_1080I_25:
printk(KERN_INFO "HDMI 1080P25\n");
davinci_writel(0x28, SYS_VPSS_CLKCTL);
dispc_reg_out(VENC_VMOD, 0x0183 );
dispc_reg_out(VENC_XHINTVL,440);
break;

case HDMI_480I:
case HDMI_576I:
case HDMI_1080P_60:
case HDMI_1080P_50:
printk("Can't support hdmi mode[%d]\n",hdmi_mode);
break;

default:
break;
}

dispc_reg_out(VENC_OSDCLK0, 0);
dispc_reg_out(VENC_OSDCLK1, 1);
dispc_reg_out(VENC_OSDHADV, 0);

davinci_writel(mode_info->left_margin,
(DM365_OSD_REG_BASE + OSD_BASEPX));
davinci_writel(mode_info->upper_margin,
(DM365_OSD_REG_BASE + OSD_BASEPY));

dispc_reg_merge(VENC_YCCCTL, (1<<0), (1<<0)); // Embedded Syn

//
//dispc_reg_merge(VENC_VDPRO, (1<<8), (1<<8)); // Color Bar
//dispc_reg_out(VENC_SYNCCTL, (VENC_SYNCCTL_SYEV | VENC_SYNCCTL_SYEH)); // External Sync
//dispc_reg_out(VENC_LCDOUT, 0x1);
}

Hi,

Firstly, I am really thank for your quick response. I have one more question: this code may use for embedded sync, so what is difference between embedded sync and non embedded sync setting? Now i am working with non embedded sync, can you give me a hint about that. sorry I am a newbie in this field. 

thanks a lot.

Just remove "dispc_reg_merge(VENC_YCCCTL, (1<<0), (1<<0)); // Embedded Syn"

^^;

Hi, I read your code and make a reference to VPBE material, I think you are correct. But I don't know why it still not work in my case.

Did we need some setting relate to LCD or something else beside VPBE register? I already check Vsync, Hsync, Pixel Clock, and data Yout Cout (by oscila), I saw some signal out and they look like correct. Do you have some others hint for my problems?

Thanks for your useful help! 

I modified the video HD loop back firmware test of Appro to apply for digital out testing. The original version of this test just support component analog 720p.

the below code is my setting for VPBE:

static void vpbe_init( )
{
Uint32 video_buffer = DDR_BASE + ( DDR_SIZE / 2 );
Uint32 basep_x;
Uint32 basep_y;
Uint32 width;
Uint32 height;
Uint32 test;

width = 1280;
height = 720;

/*
* Setup clocking / DACs
*/
VDAC_CONFIG = 0x081141EF; // Take DACs out of power down mode, enable HD component out
VPSS_CLKCTL = 0x00000038; // Enable DAC and VENC clock, use PLL2
//VPSS_CLKCTL = 0x00000028; // Enable DAC and VENC clock, use PLL2
// Select EXTCLK as video clock source
VPSS_VPBE_CLK_CTRL = 0x00000011; // Select enc_clk*1, turn on VPBE clk
//VPSS_VPBE_CLK_CTRL = 0x00000019; // Select enc_clk*1, turn on VPBE clk
VENC_CLKCTL = 0x00000011; // Enable venc & digital LCD clock
//VENC_CLKCTL = 0x00000010; // Enable venc & digital LCD clock
VENC_XHINTVL = 0x00000000; // Extend standard 720P horizontal timing

/*
* Setup OSD
*/

OSD_MODE = 0x00fc; // Blackground color blue using clut in ROM0
OSD_OSDWIN0MD = 0x0000; // Disable both osd windows and cursor window
OSD_OSDWIN1MD = 0x0000;
OSD_RECTCUR = 0x0000;
OSD_EXTEND_MODE = 0x0000;

OSD_VIDWIN0OFST = 0x1000 | width >> 4;
OSD_VIDWINADH = 0x0000;
OSD_OSDWIN0ADL = 0x0000;
//OSD_BASEPX = 0x0000;
//OSD_BASEPY = 0x0000;
OSD_BASEPX = BASEX720P;
OSD_BASEPY = BASEY720P;

//OSD_VIDWIN0XP = 0x0100;
//OSD_VIDWIN0YP = 0x0000;
OSD_VIDWIN0XP = 220;
OSD_VIDWIN0YP = 25;
OSD_VIDWIN0XL = width;
OSD_VIDWIN0YL = height;

//OSD_OSDWIN0XP = 220;
//OSD_OSDWIN0YP = 25;
//OSD_OSDWIN0XL = DISP_XRES720P;
//OSD_OSDWIN0YL = DISP_YRES720P;

OSD_VIDWINMD = 0x00000001; // Disable vwindow 1 and enable vwindow 0
// Frame mode with no up-scaling
VENC_VDPRO = 0x0000; // Normal mode, not colorbars
VENC_DACTST = 0x0000; // Power on DACs
VENC_DACSEL = 0x0543; // Component out on DACs

// Timing
VENC_HSPLS=0x50;
VENC_HINTVL = 1280 + 300 + 70 - 1;
VENC_HSTART=300;
VENC_HVALID=1280;

VENC_VSPLS=0x5;
VENC_VINTVL = 720 + 26 + 3;
VENC_VSTART=26;
VENC_VVALID=720;
// ~Timing

VENC_DCLKCTL = 0x0800; // 0x8000; 0x0800; 0x8800
VENC_DCLKPTN0 = 0x0001;

//VPSS_MISR_CTRL = 0x0003;
VENC_VIOCTL = 0x2000; // 0x2000 - 0x6000
VENC_LCDOUT = 0x0001; // 0x0001
VENC_SYNCCTL = 0x0103; // 0x000f 0x0003

VENC_OSDCLK0 = 0x00000000;
VENC_OSDCLK1 = 0x00000001; // 0x00000003
VENC_OSDHADV = 0;
VENC_VMOD = 0x05c1; // 0x05c3 - 0x0dc1 - 0x0111 - 0x1c3
//VENC_YCCCTL = 0x02; // add for embedded sync

VENC_YCOLVL = 0x00000000;

//VENC_SYNCCTL = (VENC_SYNCCTL_SYEV | VENC_SYNCCTL_SYEH | VENC_SYNCCTL_HPL | VENC_SYNCCTL_VPL);
// ~Bioz
}

It is also similar to your setting in kernel.