AM1705 GEL Script Error when Powering EMIFA

/*
 * boot.c
 *
 *  Created on: 6 Oct 2016
 *      Author: Haydn
 */

extern void main(void);


void boot(void)
{
  asm(" .global STACKStart");
  asm(" .global _stack");
  asm(" .global main");
	asm(" NOP");
  asm(" MRS  r0, cpsr");
  asm(" BIC  r0, r0, #0x1F");       // CLEAR MODES
  asm(" ORR  r0, r0, #0x13");       // SET SUPERVISOR mode
  asm(" ORR  r0, r0, #0xC0");       // Disable FIQ and IRQ
  asm(" MSR  cpsr, r0");
  asm(" NOP");

  // Set the IVT to low memory, leave MMU & caches disabled
  asm(" MRC  p15,#0,r0,c1,c0,#0");
  asm(" BIC  r0,r0,#0x00002300");
  asm(" BIC  r0,r0,#0x00000087");
  asm(" ORR  r0,r0,#0x00000002");
  asm(" ORR  r0,r0,#0x00001000");
  asm(" MCR  p15,#0,r0,c1,c0,#0");
  asm(" NOP");

  // Setup the stack pointer
  asm(" LDR  sp,_stack");
  asm(" SUB  sp,sp,#4");
  asm(" BIC  sp, sp, #7");

  // Call to main entry point
  main();

  asm("_stack:");
  asm(" .word STACKStart");
}

/*
 * gel_rewrite.c
 *
 *  Created on: 6 Oct 2016
 *      Author: Haydn
 */

#include "reg_map.h"



int Sys_Config(void){
	KICK0R = 0x83e70b13;
	KICK1R = 0x95a4f1e0;

	PINMUX0 = 0x11112100;  	// EMIFB and RTCK
	PINMUX1 = 0x11111111;  	// EMIFB
	PINMUX2 = 0x01111111;  	// EMIFB
	PINMUX3 = 0x00000000;  	// Reserved
	PINMUX4 = 0x00000000;  	// Reserved
	PINMUX5 = 0x11111110;  	// EMIFB
	PINMUX6 = 0x11111111;  	// EMIFB
	PINMUX7 = 0x11111111; 	// EMIFB and SPI0
	PINMUX8 = 0x20011100;  	// UART2, BOOT7 and UART0
	PINMUX9 = 0x00000002;  	// UART2
	PINMUX10 = 0x00000000;  // No Use
	PINMUX11 = 0x00081188;  // UART1
	PINMUX12 = 0x88808800;  // GPIO
	PINMUX13 = 0x11088888;  // EMIFA
	PINMUX14 = 0x00111111;  // EMIFA
	PINMUX15 = 0x10000000;  // EMIFA
	PINMUX16 = 0x00000001;  // EMIFA
	PINMUX17 = 0x00011000;  // EMIFA
	PINMUX18 = 0x00110010;  // EMIFA
	PINMUX19 = 0x00000001;  // EMIFA

	return 0;
}


int Setup_PLL(void){
	int i = 0;
	unsigned int CLKMODE = 0;
	unsigned int PLLM = 24;
	unsigned int POSTDIV = 1;
	unsigned int PLLDIV3 = 2;
	unsigned int PLLDIV5 = 2;
	unsigned int PLLDIV7 = 5;

	PLL0_PLLCTL &= 0xFFFFFFFE;			// Clear PLLEN
	PLL0_PLLCTL &= 0xFFFFFFF7;			// Clear PLLRST

	for (i = 0; i < 4; i++){			// Wait 4 OSCIN cycles to confirm
		;
	}


	PLL0_PLLCTL &= 0xFFFFFEFF;			// Clear CLKMODE to select crystal
	PLL0_PLLCTL &= 0xFFFFFFDF;			// Clear PLLENSRC


	PLL0_PLLCTL &= 0xFFFFFFF7; 			// Clear PLLRST

	PLL0_PLLCTL &= 0xFFFFFFFD;			// Clear PLLPWRDWN

	PLL0_PLLM |= PLLM;					// Set PLLM to 24 for 600MHz clock

	PLL0_POSTDIV = (0x8000 | POSTDIV);	// Set POSTDIV to 1 for /2

	while (PLL0_PLLSTAT & 0x1){			// Check GOSTAT bit if transition is ongoing
		;
	}

	PLL0_PLLDIV3 = (0x8000 | PLLDIV3);	// Set the EMIFA Clock
	PLL0_PLLDIV5 = (0x8000 | PLLDIV5);	// Set the EMIFB Clock

	PLL0_PLLCMD = 0x1;					// Set the GOSET bit to initiate transition

	while (PLL0_PLLSTAT & 0x1){			// Wait for GOSTAT bit to clear
			;
		}


	PLL0_PLLCTL |= 0x8;

	for (i = 0; i < 2400; i++){			// Wait for PLL to lock
		;
	}

	PLL0_PLLCTL |= 0x1;

	return 0;
}

int PSC0_lPSC_Enable(uint32_t LPSC_num){

	while (PSC0_PTSTAT & 0x1){			// Wait for other transitions
		;
	}

	*(unsigned int*) (PSC0_MDCTL + 4 * LPSC_num) |= 0x3;
	// Enable the module

	PSC0_PTCMD = 0x1;					// Initialise the transition

	while (PSC0_PTSTAT & 0x1) {
		; 								// Wait for power state transition to finish
	}

	return 0;
}

int PSC1_lPSC_Enable(uint32_t LPSC_num){

	while (PSC1_PTSTAT & 0x1){			// Wait for other transitions
		;
	}

	*(unsigned int*) (PSC1_MDCTL + 4 * LPSC_num) |= 0x3;
	// Enable the module

	PSC1_PTCMD = 0x1;					// Initialise the transition

	while (PSC1_PTSTAT & 0x1) {
		; 								// Wait for power state transition to finish
	}

	return 0;
}


int Setup_PSC(void){

	PSC0_lPSC_Enable(0);		// EDMA Channel Controller
	PSC0_lPSC_Enable(1);		// EDMA Transfer Controller 0
	PSC0_lPSC_Enable(2);		// EDMA Transfer Controller 1
	PSC0_lPSC_Enable(3);		// EMIFA
	PSC0_lPSC_Enable(4);		// SPI0
	PSC0_lPSC_Enable(5);		// MMC
	PSC0_lPSC_Enable(6);		// ARM Interrupt Controller
	// Number 7 is the ARM core it will be enabled later
	PSC0_lPSC_Enable(9);		// UART0
	PSC0_lPSC_Enable(10);		// SCR0
	PSC0_lPSC_Enable(11);		// SCR1
	PSC0_lPSC_Enable(12);		// SCR2
	PSC0_lPSC_Enable(13);		// PRU

	PSC1_lPSC_Enable(1);		// USB0

	PSC1_lPSC_Enable(3);		// GPIO

	PSC1_lPSC_Enable(5);		// EMAC
	PSC1_lPSC_Enable(6);		// EMIFB
	PSC1_lPSC_Enable(7);		// MCASP0
	PSC1_lPSC_Enable(8);		// MCASP1

	PSC1_lPSC_Enable(10);		// SPI1
	PSC1_lPSC_Enable(11);		// I2C1
	PSC1_lPSC_Enable(12);		// UART1
	PSC1_lPSC_Enable(13);		// UART2

	PSC1_lPSC_Enable(17);		// EHRPWM

	PSC1_lPSC_Enable(20);		// ECAP
	PSC1_lPSC_Enable(21);		// EQEP

	PSC1_lPSC_Enable(24);		// SCR8
	PSC1_lPSC_Enable(25);		// SCR7
	PSC1_lPSC_Enable(26);		// SCR12

	PSC1_lPSC_Enable(31);		// Shared RAM



	return 0;
}

/*
 * main.c
 */



#include "reg_map.h"

int main(void) {
	
	Sys_Config();
	Setup_PLL();
	Setup_PSC();







	return 0;
}