AM5716: DSP access to GPMC

Hiroyasu Tazawa1

Guru 12350 points

Part Number: AM5716

Hi,

Let me talk about AM5716.

My customer want to use C66DSP for calculation.

They consider this system.
It need calculation of real time.

and We think Sequence is below:

(1)FPGA send data via GPMC to AM57x
(2)Calculation using C66DSP
(3)C66DSP feedback to FPGA

and We think Data Flow in AM57x is below:

(a)GPMC get Data and transfer data via EDMA
(b)After transfer comleate, EDMA issues an interrupt to the DSP.
(c)DSP calculate
(d)After compleate of calculation, DSP send result data to GPMC
(e)GPMC send Data to FPGA

so I have a few question.

(i)I think C66DSP can not access to GPMC directly. but C66DSP access EDMA.
Because It is described

This understanding is correct?

(ii)I beleive AM57x has capability for this system using only GPMC
　 and C66DSP and EDMA After initialization.
It means we do not want to use M4 and A15. Because of realtime system.
Can you give me any advice whether this system is feasible? and If you have other idea for realtime system using AM5716, Please let me know.

Best regards
Hiroyasu

over 6 years ago

0 Biser Gatchev-XID over 6 years ago

TI__Guru**** 393215 points

The factory team have been notified. They will respond here.

0 Yordan Kovachev over 6 years ago

TI__Guru**** 161600 points

Hi Hiroyasu,

Here is what I can answer of your questions:

(i)I think C66DSP can not access to GPMC directly. but C66DSP access EDMA.
Because It is described
his understanding is correct?

The connectivity matrix in the TRM (Section 14.2 L3_MAIN Interconnect) is NOT quite clear about that. But in general here is the case:
DSP1 has MDMA & DMA ports. There is an L3 NoC path between GPMC and DSPI1_MDMA and DSP1_DMA ports.
The DSP_CFG port does NOT have an L3 path to GPMC. To get further info on DSP ports you can have a look at Figure 5-1. DSP Subsystem Highlight in the TRM. You can see which modules you can access through DSP_CFG port in Table 2-1. L3_MAIN Memory Map and Table Table 2-10. DSP Memory Map; search forconfiguration space addresses.

Also all DSP1 ports have L3 NoC paths to the EDMA TPCC & EDMA TC1 and EDMA TC2. This means that the DSP also has a configuration path to EDMA, meaning that it can access EDMA configuration registers.

(ii)I beleive AM57x has capability for this system using only GPMC
　 and C66DSP and EDMA After initialization.
It means we do not want to use M4 and A15. Because of realtime system.
Can you give me any advice whether this system is feasible?

I think the AM57xx devices should be able to match your requirements. I'll let the factory team elaborate here (if there is a better solution).

Best Regards,
Yordan

0 Hiroyasu Tazawa1 over 6 years ago in reply to Yordan Kovachev

Guru 12350 points

Hi, Yordan

Thank you for your reply!!

I understood DSP can not access via DSP_CFG port.
But DSP can access EDMA Because of L3 NoC paths.

and If factory team has any good better ideas, Please let me know !!

Best Regards
Hiroyasu

0 jian35385 over 6 years ago in reply to Yordan Kovachev

TI__Mastermind 23125 points

Hiroyasu and Yordan,

I confirm Yordan's notes that Figure 5-1 will be a good assistance to read the connectivity matrix in Sec 14.2, where in Figure 14-3:
- DSP1_MDMA refers to the "CPU Master" port in Figure 5-1;
- DSP1_DMA port refers to "DMA Master" port as in Figure 5-1.
The DSP subsystem in AM5716 includes a built-in EDMA engine, that is why there is a also DMA master port from the DSPSS.

For your application, you can either use CPU directly access the GPMC address space (L3_MAIN base address of DSP view, + GPMC address offset); or your can use DMA to move data to the L2 SRAM in the DSP subsystem. there is 288KB L2/Cache that you may configure up to 256KB as SRAM.

If your data is larger, you may consider first DMA to the DDR then access by C66 DSP.

Let us know if you need further assistance finding the GPMC address or re-architect data flow.

regards
Jian

0 Hiroyasu Tazawa1 over 6 years ago in reply to jian35385

Guru 12350 points

Hi, Jian

Thank you for your reply !

I do not clear about GPMC access from DSP.

What is DSP1_CFG in Figure 14-3 ?
I thought DSP1_CFG means register access.
but it was wrong, DSP can access L3_MAIN base address of DSP view + GPMC address offset.
I do not understand what is DSP1_CFG and what is limited ?

Best Regards
Hiroyasu

0 jian35385 over 6 years ago in reply to Hiroyasu Tazawa1

TI__Mastermind 23125 points

Hiroyasu,

The secret is still in Figure 5-1 :), where you can see that the DSP CFG Master port is only accessible by the DSP via the EMC port, where the explanation of the EMC port is also in Sec 5.1.1:
"The External Memory Controller (EMC) is a bridge from the C66x CorePac to the rest of the DSP subsystem and device. It has :
– a 32-bit configuration port (CFG) providing access to local subsystem resources (like DSP_EDMA, DSP_SYSTEM, and so forth) or to L3_MAIN resources accessible via the CFG address range."

This port is intended to be used for DSP to reach the SOC config register space, evidenced in the Figure 14-3, where you can see the DSP1_CFG can only reach EDMA registers, L4_PER1_P1, which connects so CFG ports of some peripherals as well as some slow interfaces (I2C, UART etc., see Figure 14-9).

DSP access to GPMC, should use the L3_MAIN (0x1400 0000) base address. the transaction actually goes through the XMC port in Figure 5-1.

If you use DMA to write GPMC data to the DSP L2 SRAM, the incoming transaction will go through the "L2 Slave" port to the EMC-SDMA port.

let me know if these explanations make sense.

regards
jian

0 Hiroyasu Tazawa1 over 6 years ago in reply to jian35385

Guru 12350 points

Hi, Jian

Thank you for your reply!
I got it.

Best Regards
hiroyasu

Processors

Processors forum

AM5716: DSP access to GPMC