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AM1806: Evaluating the DDR_DQGATE0 and DDR_DQGATE1

Part Number: AM1806

Hello,

Can I ask a couple of questions below?:

 

Q1. Please find the DDR_DQGATE1 waveform and it has distortions at the rising and the falling edges. Do you think this is harmful or not?

Do you think this level of the distortion could bring erroneous behaviors?

 

 

Q2. Could you please give a brief explanation how the DDR_DQGATE1 is utilized?

My customer requested this to understand your answer to the Q1.

Ex) A timer counts the DDR_DQGATE0 to DDR_DQGATE1 delay and the delay is provided for DDR_DQS timings.

Ex) The DDR_DQGATE1 input is an asynchronous timing to trigger DDR_DQS transition.

 

 

 DDR_DQGATE0 waveform

 

DDR_DQGATE1 waveform with marks at distortions

  

 

  • Hi,

    We're looking into this.

    Best REgards,
    Yordan
  • Hi Hideaki-san,

    I'm checking into your questions.

    Does the board have a series termination resistor (10 ohm typical)? What is the drive strength?

    Regards,
    Mark
  • Hi Hideaki-san,

    Answers to your questions are below.

    Q1. 

    Yes, the DDR_DQGATE1 input is very sensitive to non-monotnonic edges. It must be free from glitches. The non-monotonic edges near the input threshold can cause glitches, and must be avoided for robust operation.

    The series termination should be placed close to the output DDR_DQGATE0 pin. Values like 10 ohms, 22 ohms, and 33 ohms can be tried.

    Q2.

    DQGATE is used to enable the READ FIFO. Routing on the board is intended to establish the round-trip delay. That is why the routed length needs to match the clock length plus the DQS length between the controller and memories.

    DDR2 does not have DLLs and adaptive timing logic like DDR3. All routes are length matched from controller to SDRAM - clock, address, command and data group signals. This input is literally the gate enable for the READ FIFO. Timing and signal integrity are important to robust DDR2 operation.

    Hope this helps,
    Mark

  • Mark,
    Thank you very much. Very clear.
  • Mark,

    Please forgive my rushing...


    Q3.
    When the signals {DDR_DQGATE0 and DDR_DQGATE1} are used, or evaluated?
    From your answer Q2, I think it is anytime when the DDR_DQS is working, but please let me confirm.


    Q4.
    Could you please help me to resolve our confusion? I think the DDR_DQS[1:0] are sufficient to control the read FIFO, but the part needs the extra signals DDR_DQGATE[1:0]? I could not clarify with its TRM.


    Q5.
    My customer would be glad if a block diagram to shows how the DDR_DQGATE1 control the read FIFO. I could not find from AM18xx TRM, but do you know? This question is related to Q3 and Q4.


    Q6.
    My customer found the waveforms look better in boot time. I was asked to explain why the waveforms are different from the question-1 waveforms when executing the user code. Do you agree it is possible if the SDCR.DDRDRIVE[1:0] are the default value zero in boot time?

     DDR_DQGATE0 waveform (when booting) - - The GND points are shifted by the voltage & time divsions are the same. 0.5V/div, 10nsec/div.

     DDR_DQGATE1 waveform (when booting)

  • Hi Hideaki-san,

    The designer for DDR is out of office this week, but I will follow up with him next week about these questions.

    Q3: We believe DQGATE is used every READ.

    Q4: DQS clocks the READ data into a FIFO. DQGATE is an enable for that FIFO to prevent glitches from clocking in garbage. Did you verify the round trip routing? Has a series resistor been tested as a solution?

    Q5: I'll ask the designer next week if any block diagram exists.

    Q6: Can the customer read these DDR registers (like SDCR.DDRDRIVE[1:0]) right after boot to compare them to how they are configuring them? The different settings may be the reason for the glitches on DQGATE1. These glitches must be avoided.

    Remind me next week if I dont get back to you with more answers.

    Hope this helps,
    Mark
  • Hideaki-san,

    We confirmed that the DQS gate only opens when receiving read data. The DQS gating signal is used to time the opening and closing of the DQS gate so that the gate is opened during read DQS preamble and closed on the last falling edge of the DQS. The gate is kept closed all other times to prevent glitches from the outside to propagate to inside the IP since DQS is used as a clock to latch read data internally.

    It is only needed for high frequency modes of operation where the frequencies, board and IO delays introduced in the DDR signal path are comparable to clock periods and have to be modeled in the macro (by looping back the DQGATE signals). The route on the board for the loop back signal should closely match the combination of the addr-control signal route and the data signal route.

    At slow frequencies the board and IO delays introduced in the DDR signal path is assumed to be considerable less than the clock period and can be neglected.

    No block diagram exists in the documentation.

    Regards,
    Mark

  • Mark,
    I'm sorry but let me correct my explanation and question as Q6-2.

    [Correction]

    The condition of the (good / no good) waveforms is not (before/after) initialization, but (Debug run / standalone).
    That is, the DDR_DQGATE waveform improved when the user program was launched by CCS debug button.

    [Common condition]

    SDCR. DDRDRIVE[1:0] = 1   ~ The half strength.

    The waveform was captured when a user program completed initializations and reach a normal operation.

    The OS is an RTOS other than TI-RTOS.

    Question 6-2:  (Let me revise my question-6)
    Could you please advice register bits which can bring a better DDR_DQGATE waveforms in debug-run only?

  • Mark-san:

    Just for reference regarding to the Q6-2.

    I asked my customer to compare the DDR registers which is listed in the TRM chapter 14.4, but no findings.

    - case1: Debug-run: The debug was launched by the bug button.

    - case-2: Standalone: The XDS probe is wired but the session disabled. Once let the target run in standalone, right-click the TargetConfigration, connect, pause the arm core. (Strictly, it is not a read fom standalone target.)

  • Mark,

    We appreciate your patience for this long thread.

    Can I ask you some more clear words to agree?

    Your post on Mar16th sounded to me that:

    - The DDR_DQGATE1 just unmask the DDR_DQS[1:0]. It doesn't clock the FIFO.  ( It doesn't latch the DDR_D[]. )

    - It is DDR_DQS[1:0] to clock or let the FIFO to latch the DDR_D[].

    Given that, although it is close to the question-1, :

    Q7. I think that the DDR_DQGATE1 glitch alone is not a problem. Do you agree?

    Q8. Is it possible for my customer to let the DDR_DQGATE1 waveform as-is? (In case there are none of data corruptions)

  • Hi Nambu-san,

    I have asked the designer your question.

    If the DQGATE1 is simply used to ungate the DQS from latching data into the FIFO, then perhaps the glitch is not a problem as long as DQS is not noisy. But if the rising edge and falling edge of DQGATE1 are also used, then the glitch could be a big problem.
    Let us wait until next week to see what the designer finds.

    Regards,
    Mark
  • Hi Nambu-san,

    As far as we know the DQGATE1 is a a level sensitive signal. It is used as one input to an AND gate where the other input is the DQS strobe. So whenever DQGATE1 is high, the AND gate allows DQS to flow through and latch data into the FIFO.

    A glitch on the DQGATE can open the AND gate. If the DQS signal is high-z when the DQGATE1 crosses the threshold to open the gate, it can transmit a glitch into the internal circuit causing the flops to latch in erroneous data.

    If the customer is confident that the DQS is static low during these non-monotonic edges on DQGATE1, then maybe they will never see any problem. But it is not recommended to have a glitch on DQGATE1.

    Do they have any scope shots showing DQS and DQGATE1 together? Does the relative timing of DQGATE1 to DQS vary from board to board?

    Was there no way to reduce or eliminate the non-monotonic edge through the drive strength setting? How is the DQGATE1 signal clean when the bootloader is running?

    Regards,
    Mark

  • Mark,

    I appreciate your reply. I will talk to my customer.