DRA712: Suggested stackup diagram with drill pairs for 10 layer PCB

Please find below the url/link to the TI Designs "Entry Level Infotainment Reference Design with Jacinto6 Entry (DRA71x)".  This reference design illustrates a low-cost 6-Layer PCB design that supports following core functionality: 100% signal breakout of Jacinto6 Entry SoC, single TPS65919 PMIC in a robust PDN that meets all power integrity recommendations, 2GBytes of DDR3L SDRAM operating up to 667MHz, and 32GBytes of eMMC Flash memory.

The PCB source file is available for downloading at the link below. The PCB stack-up & controlled impedance plan are captured in the PCB file. The via drill plan uses 3 different plated through-hole vias to keep cost low as follows: 16/8 breakout vias used underneath DRA71x for breakout, 20/10 signal vias and 24/12 power vias used outside the DRA71x footprint.

http://www.ti.com/tool/TIDEP-009