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OMAP-L137 EMIFA DQM Lines- How are they mapped in memory?

Newbie question on the EMIFA: I am using EMIF A to map to an external 16-bit Async RAM.  Beside the A[0:12] and BA[0:1] lines, the DQM's can be used as byte selects.  My question is, how are they used?  I know that in 16-bit mode:

  1. the L137's BA[1] maps to the external device's A[0]
  2. the L137's A[0:12] maps to the external device's A[1:13] respectively
  3. the L137's BA[0] maps to the external device's A[22] (or some other high order address bit- not sure which)

Where do the DQM's map?

Thanks!

  • The DQM signals should be connected to the byte enable signals on your 16-bit async RAM.  You may want to refer to the appendix in the EMIFA user guide for an example of how these are connected to SDRAM and Flash.  Your TI board schematics will also provide some examples of how they are used.

  • Thanks for your reply, Gus.

    Right.  What memory locations will toggle these lines? What is the lowest address that when you execute a read/write request, would make one of these change values?

    If I look at EMIFA user guide (SPRUFL6E) page 76, it shows something similar.  (Here, they are using additional GPIO to drive A[13:18] which I assume must be controlled outside of the EMIF.)  

    I think I understand how the A[0:12] and BA[1] lines are driven for read/write requests.  I do not understand how the DQM lines are driven.  What address would be the lowest on CS2 to drive DQM[0] high?  For example. CS2 on EMIFA has a base address of 0x6000 0000.  Would it be something like 0x6000 8000?  I am guessing this since BA[1] would map to the second bit of the mapped memory address  (0x6000 0002), then the 13 address lines would map to the 3rd bit through the 15th (0x6000 0004 through 0x6000 4000)

    Am I mis-understanding how these lines are used for 16-bit Async connections?

     

  • For 16-bit reads and writes, they will both be active during any type of access.

    For 8-bit reads, they will both be active as well.

    For 8-bit writes, only the byte to which you are writing will have the corresponding DQM active.

    Jeff

  • rusty_shackleford said:
    Right.  What memory locations will toggle these lines? What is the lowest address that when you execute a read/write request, would make one of these change values?

    Ah, I get your question now...

    The DQM signals toggle depending on the size of the access and the size of the EMIF bus.  For example, if your EMIF bus is16-bits in size and you perform a 32-bit access. you will see two 16-bit accesses on the bus with both DQM pins asserted (low).  If your access is 8 bits, then DQM0 will go low if the LSB of the address is 0 or DQM1 will go low if the LSB is 1.  If your EMIF bus is 8-bit in size, then only DQM0 should toggle and it will toggle for every access.  Note that 8-bit async memories will not have a byte select input (redundant), so in this case DQM is used only special cases (e.g. as a strobe when connecting to the host port of another device).

    rusty_shackleford said:
    What address would be the lowest on CS2 to drive DQM[0] high?  For example. CS2 on EMIFA has a base address of 0x6000 0000.  Would it be something like 0x6000 8000?  I am guessing this since BA[1] would map to the second bit of the mapped memory address  (0x6000 0002), then the 13 address lines would map to the 3rd bit through the 15th (0x6000 0004 through 0x6000 4000)

    You got the last part right.  The EMIFA module actually has A[23:0] pins, however, only A[12:0] are pinned out on this device.  The pins that are no pinned out map to the remaining bits in your addressing example.