AM5718: PRU debug issue

Hi Garrett,

But does it put the PRU's in free run?

Blake

Hello Blake, I fixed it.

There were two problems:

1) I was loading the PRU memory with firmware while the module was not being clocked.
When the clocking was turned back on, it would be full of random bits.
The PRU must be not running, but clocked in order for other hosts to load its memory area.

2) I simply needed to turn on a bit in PRU_CONTROL for the correct PRU (bit 1, ENABLE, page 7377 of the TRM). This makes the PRU run. This was what I wanted to know how to do.

Now, I can launch the PRU’s from the DSP code. This may simplify things for our team members on the Linux side of things.
They are not at a point where I could ask them to load the PRU’s for me either.

The final code:

#include <stdio.h>
#include <ti/csl/soc/am572x/src/cslr_l4per_cm_core_component.h>
#include <ti/csl/soc/am572x/src/cslr_control_core_pad_io.h>
#include <ti/csl/soc/am572x/src/cslr_soc.h>
#include "../PRU_adc/Hex/PRU_adc.hex"


void PRU_init(void)
{
CSL_l4per_cm_core_componentRegs *l4PerCmReg = (CSL_l4per_cm_core_componentRegs *) CSL_DSP_L4PER_CM_CORE_REGS;
CSL_control_core_pad_ioRegs *controlCorePadReg = (CSL_control_core_pad_ioRegs *) CSL_DSP_CORE_PAD_IO_REGISTERS_REGS;
volatile unsigned int *pruss1_syscfg = ((volatile unsigned int *)0x4B226004);
volatile unsigned int *pruss1_pru0_control = ((volatile unsigned int *)0x4B222000);

//Set pin mux mode to connect the PRU to external GPIO pins and enable inputs
CSL_FINS(controlCorePadReg->PAD_VIN1A_D5, CONTROL_CORE_PAD_IO_PAD_VIN1A_D5_VIN1A_D5_MUXMODE, 13U); // SPI CS
CSL_FINS(controlCorePadReg->PAD_VIN1A_D5, CONTROL_CORE_PAD_IO_PAD_VIN1A_D5_VIN1A_D5_INPUTENABLE, CSL_CONTROL_CORE_PAD_IO_PAD_VIN1A_D5_VIN1A_D5_INPUTENABLE_DISABLE); // SPI CS
CSL_FINS(controlCorePadReg->PAD_VIN1A_D6, CONTROL_CORE_PAD_IO_PAD_VIN1A_D6_VIN1A_D6_MUXMODE, 13U); // SPI CLK
CSL_FINS(controlCorePadReg->PAD_VIN1A_D6, CONTROL_CORE_PAD_IO_PAD_VIN1A_D6_VIN1A_D6_INPUTENABLE, CSL_CONTROL_CORE_PAD_IO_PAD_VIN1A_D6_VIN1A_D6_INPUTENABLE_DISABLE); // SPI CLK
CSL_FINS(controlCorePadReg->PAD_VIN1A_D7, CONTROL_CORE_PAD_IO_PAD_VIN1A_D7_VIN1A_D7_MUXMODE, 12U); // SPI Data
CSL_FINS(controlCorePadReg->PAD_VIN1A_D7, CONTROL_CORE_PAD_IO_PAD_VIN1A_D7_VIN1A_D7_INPUTENABLE, CSL_CONTROL_CORE_PAD_IO_PAD_VIN1A_D7_VIN1A_D7_INPUTENABLE_ENABLE); // SPI Data
//TODO maybe disable weak pull up/down on these as well

//Disable clock to PRUSS1 module (containing 2 PRU units)
CSL_FINST(l4PerCmReg->CM_L4PER2_PRUSS1_CLKCTRL_REG, L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS1_CLKCTRL_REG_MODULEMODE, DISABLED);

//Enable clock to PRUSS1 module (containing 2 PRU units)
CSL_FINST(l4PerCmReg->CM_L4PER2_PRUSS1_CLKCTRL_REG, L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS1_CLKCTRL_REG_MODULEMODE, ENABLE);

//memcpy firmware to the correct PRU instruction area of memory
memcpy((void *)CSL_DSP_PRUSS1_U_INST_RAM0_12KB_REGS, PRU_adc_image_0, sizeof(PRU_adc_image_0));

//Take PRU out of standby
*pruss1_syscfg = (*pruss1_syscfg & 0xFFFFFFF0) | (1<<2) | 1;
*pruss1_pru0_control = (*pruss1_pru0_control & 0xFFFFFFFD) | (1<<1);
}


int main(void)
{
PRU_init();
while(1);
return 0;
}

Also, page 7341 of the TRM gives a sequence for idling the PRU’s and for taking them out of idle.
It makes no mention of the PRU_CONTROL register or the run bit (enable). I think this is a deficiency in the documentation.