This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

  • Resolved

AM5718: PRU debug issue

Expert 5910 points

Replies: 7

Views: 578

Part Number: AM5718

I have been doing DSP type development, trying to get ready before we produce our first board.

 

I have an AM5728 IDK board. I am doing some work to get the PRU to grab data from digitizers. Right now, this is a single ADS7883 ADC, but it will turn into an ADS9234.

I’m using PRU0 in the first ICSS unit. I have good PRU firmware and I generated an image:

 

const uint32_t PRU_adc_image_0[] = {

0x240000c0,

0x24010080,

0x0504e0e2,

 

I have been trying to get it to run while debugging from the first DSP c66x core:

(DSP code)

void PRU_init(void)

{

    CSL_l4per_cm_core_componentRegs *l4PerCmReg = (CSL_l4per_cm_core_componentRegs *) CSL_DSP_L4PER_CM_CORE_REGS;

    CSL_control_core_pad_ioRegs *controlCorePadReg = (CSL_control_core_pad_ioRegs *) CSL_DSP_CORE_PAD_IO_REGISTERS_REGS;

//    volatile unsigned int *pruss_cgr = ((volatile unsigned int *)0x4B226010);

    volatile unsigned int *pruss_syscfg = ((volatile unsigned int *)0x4B226004);

 

    //Set pin mux mode to connect the PRU to external GPIO pins and enable inputs

    CSL_FINS(controlCorePadReg->PAD_VIN1A_D5, CONTROL_CORE_PAD_IO_PAD_VIN1A_D5_VIN1A_D5_MUXMODE, 13U); // SPI CS

    CSL_FINS(controlCorePadReg->PAD_VIN1A_D5, CONTROL_CORE_PAD_IO_PAD_VIN1A_D5_VIN1A_D5_INPUTENABLE, CSL_CONTROL_CORE_PAD_IO_PAD_VIN1A_D5_VIN1A_D5_INPUTENABLE_DISABLE); // SPI CS

    CSL_FINS(controlCorePadReg->PAD_VIN1A_D6, CONTROL_CORE_PAD_IO_PAD_VIN1A_D6_VIN1A_D6_MUXMODE, 13U); // SPI CLK

    CSL_FINS(controlCorePadReg->PAD_VIN1A_D6, CONTROL_CORE_PAD_IO_PAD_VIN1A_D6_VIN1A_D6_INPUTENABLE, CSL_CONTROL_CORE_PAD_IO_PAD_VIN1A_D6_VIN1A_D6_INPUTENABLE_DISABLE); // SPI CLK

    CSL_FINS(controlCorePadReg->PAD_VIN1A_D7, CONTROL_CORE_PAD_IO_PAD_VIN1A_D7_VIN1A_D7_MUXMODE, 12U); // SPI Data

    CSL_FINS(controlCorePadReg->PAD_VIN1A_D7, CONTROL_CORE_PAD_IO_PAD_VIN1A_D7_VIN1A_D7_INPUTENABLE, CSL_CONTROL_CORE_PAD_IO_PAD_VIN1A_D7_VIN1A_D7_INPUTENABLE_ENABLE); // SPI Data

    //TODO maybe disable weak pull up/down on these as well

 

    //Disable clock to PRUSS1 module (containing 2 PRU units)

    CSL_FINST(l4PerCmReg->CM_L4PER2_PRUSS1_CLKCTRL_REG, L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS1_CLKCTRL_REG_MODULEMODE, DISABLED);

 

    //memcpy firmware to the correct PRU instruction area of memory

    memcpy((void *)CSL_DSP_PRUSS1_U_INST_RAM0_12KB_REGS, PRU_adc_image_0, sizeof(PRU_adc_image_0));

 

    //Enable clock to PRUSS1 module (containing 2 PRU units)

    CSL_FINST(l4PerCmReg->CM_L4PER2_PRUSS1_CLKCTRL_REG, L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS1_CLKCTRL_REG_MODULEMODE, ENABLE);

 

    //Take PRU out of standby

    *pruss_syscfg = (*pruss_syscfg & 0xFFFFFFF0) | (1<<2) |1;

}

 

The firmware does appear in the instruction memory for the correct PRU after I execute this.

However, it tends to say that the module is in standby still in the CM_L4PER2_PRUSS1_CLKCTRL register (0x00040000 bit).

This changed after I connected the debugger to the PRU and then back to the DSP.

Still, it does not run. In fact, it says that the two PRU units on ICSS1 are (Suspended) in the eclipse debug window.

I feel that it is the IDE that is holding the two units in suspension. Am I right? What to do?

 


Thanks!

 

Blake

Best Regards, Blake

  • The RTOS team have been notified. They will respond here.

     

    Best Regards
    Biser
  • In reply to Biser Gatchev-XID:

    Blake,

    Have you tried to use the APIs from PRUSS driver processors.wiki.ti.com/.../Processor_SDK_RTOS_PRUSS

    /* Creates handle for PRUICSS instance */
    handle = PRUICSS_create(pruss_config,instance);

    int32_t PRUICSS_setPRUBuffer( PRUICSS_Handle handle,
    uint32_t pruNum,
    void *buffer,
    uint32_t numBytes
    )

    int32_t PRUICSS_pruExecProgram(PRUICSS_Handle handle,int32_t pruNum)

    And do you use the '--array' option in PRU compiler to generate the firmware header file?

    Regards,
    Garrett
  • In reply to Garrett Ding:

    I am the originator of the question.
    I do use the --array option.
  • In reply to Garrett Ding:

    Hi Garrett,

    Is there a GEL file that would allow the C6xxx to be debugged while putting the PRU's in RUN mode?

    Thanks!

    Blake

    Best Regards, Blake

  • In reply to Blake Carpenter:

    Blake,

    The GEL function 'DSPSSClkEnable(uint32_t cpu_num)' in AM572x_multicore_reset.gel (ccsv8\ccs_base\emulation\boards\am572x\gel) associated with ARM core brings DSP out of reset. Is this what you are looking for?

    Regards,
    Garrett
  • In reply to Garrett Ding:

    Hi Garrett,

    But does it put the PRU's in free run?

    Blake

    Best Regards, Blake

  • In reply to Blake Carpenter:

    Hello Blake, I fixed it.

    There were two problems:

    1) I was loading the PRU memory with firmware while the module was not being clocked.
    When the clocking was turned back on, it would be full of random bits.
    The PRU must be not running, but clocked in order for other hosts to load its memory area.

    2) I simply needed to turn on a bit in PRU_CONTROL for the correct PRU (bit 1, ENABLE, page 7377 of the TRM). This makes the PRU run. This was what I wanted to know how to do.

    Now, I can launch the PRU’s from the DSP code. This may simplify things for our team members on the Linux side of things.
    They are not at a point where I could ask them to load the PRU’s for me either.

    The final code:

    #include <stdio.h>
    #include <ti/csl/soc/am572x/src/cslr_l4per_cm_core_component.h>
    #include <ti/csl/soc/am572x/src/cslr_control_core_pad_io.h>
    #include <ti/csl/soc/am572x/src/cslr_soc.h>
    #include "../PRU_adc/Hex/PRU_adc.hex"


    void PRU_init(void)
    {
    CSL_l4per_cm_core_componentRegs *l4PerCmReg = (CSL_l4per_cm_core_componentRegs *) CSL_DSP_L4PER_CM_CORE_REGS;
    CSL_control_core_pad_ioRegs *controlCorePadReg = (CSL_control_core_pad_ioRegs *) CSL_DSP_CORE_PAD_IO_REGISTERS_REGS;
    volatile unsigned int *pruss1_syscfg = ((volatile unsigned int *)0x4B226004);
    volatile unsigned int *pruss1_pru0_control = ((volatile unsigned int *)0x4B222000);

    //Set pin mux mode to connect the PRU to external GPIO pins and enable inputs
    CSL_FINS(controlCorePadReg->PAD_VIN1A_D5, CONTROL_CORE_PAD_IO_PAD_VIN1A_D5_VIN1A_D5_MUXMODE, 13U); // SPI CS
    CSL_FINS(controlCorePadReg->PAD_VIN1A_D5, CONTROL_CORE_PAD_IO_PAD_VIN1A_D5_VIN1A_D5_INPUTENABLE, CSL_CONTROL_CORE_PAD_IO_PAD_VIN1A_D5_VIN1A_D5_INPUTENABLE_DISABLE); // SPI CS
    CSL_FINS(controlCorePadReg->PAD_VIN1A_D6, CONTROL_CORE_PAD_IO_PAD_VIN1A_D6_VIN1A_D6_MUXMODE, 13U); // SPI CLK
    CSL_FINS(controlCorePadReg->PAD_VIN1A_D6, CONTROL_CORE_PAD_IO_PAD_VIN1A_D6_VIN1A_D6_INPUTENABLE, CSL_CONTROL_CORE_PAD_IO_PAD_VIN1A_D6_VIN1A_D6_INPUTENABLE_DISABLE); // SPI CLK
    CSL_FINS(controlCorePadReg->PAD_VIN1A_D7, CONTROL_CORE_PAD_IO_PAD_VIN1A_D7_VIN1A_D7_MUXMODE, 12U); // SPI Data
    CSL_FINS(controlCorePadReg->PAD_VIN1A_D7, CONTROL_CORE_PAD_IO_PAD_VIN1A_D7_VIN1A_D7_INPUTENABLE, CSL_CONTROL_CORE_PAD_IO_PAD_VIN1A_D7_VIN1A_D7_INPUTENABLE_ENABLE); // SPI Data
    //TODO maybe disable weak pull up/down on these as well

    //Disable clock to PRUSS1 module (containing 2 PRU units)
    CSL_FINST(l4PerCmReg->CM_L4PER2_PRUSS1_CLKCTRL_REG, L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS1_CLKCTRL_REG_MODULEMODE, DISABLED);

    //Enable clock to PRUSS1 module (containing 2 PRU units)
    CSL_FINST(l4PerCmReg->CM_L4PER2_PRUSS1_CLKCTRL_REG, L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS1_CLKCTRL_REG_MODULEMODE, ENABLE);

    //memcpy firmware to the correct PRU instruction area of memory
    memcpy((void *)CSL_DSP_PRUSS1_U_INST_RAM0_12KB_REGS, PRU_adc_image_0, sizeof(PRU_adc_image_0));

    //Take PRU out of standby
    *pruss1_syscfg = (*pruss1_syscfg & 0xFFFFFFF0) | (1<<2) | 1;
    *pruss1_pru0_control = (*pruss1_pru0_control & 0xFFFFFFFD) | (1<<1);
    }


    int main(void)
    {
    PRU_init();
    while(1);
    return 0;
    }

    Also, page 7341 of the TRM gives a sequence for idling the PRU’s and for taking them out of idle.
    It makes no mention of the PRU_CONTROL register or the run bit (enable). I think this is a deficiency in the documentation.

    Best Regards, Blake

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.