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XEVMK2LX: 66AK2L06 JESD DFE configuration and limitations

Part Number: XEVMK2LX
Other Parts Discussed in Thread: 66AK2L06, RFSDK, LMK04828, CDCM6208, TM4C1294NCPDT

Hi Joe,

What is the DFE input rate limit for K2L processor. Will it support 30.72MHz?

I had sent a query

https://e2e.ti.com/support/processors/f/791/t/717739

For the same design, would like to know the Maximum and minimum supported data rate on DFE IQN2 side. Will it support 30.72MHz.

We are designing a LTE enodeB with 20MHz BW and 30.72MHz sampling rate.

But we are not sure whether DFE supports this low rate of 30.72MHz.

We are interfacing AFE7xxx for 4Tx4R configuration for LTE20. The AFE7xxx has 8 serdes JESD lanes. But K2L has 4 JESD Lanes. 

The JESD lanes 5-8 on AFE7xxx is not used in the design.

Kindly advice the required sampling rates from AFE7xxx to DFE IQN2 for 4Tx4R LTE 20 MHz bandwidth. We are require to use 30.72MHz at DFE IQN2.

Kindly reply...

Regards,

Sumathi

  • Hello,
    In the 66aK2L06 or TCI6630K2L the DFE and IQNet User Guides, describe the IQNet - to /from - DFE Baseband rate.
    1.92, 3.84, 7.68, 15.36, 30.72, (non LTE /WCDMA rates) 61.44, 92.16, 122.88e6.
    DFE User Guide " www.ti.com/.../spruhx8a.pdf""
    Please search for "RFSDK" for the software to control IQNet and DFE

    You would typically for a system that has DPD or even adding multicarrier support, you would use a 61.44, 122.88, Msps complex data stream for Tx.
    In the Rx direction normally a 61.44Msps stream is used. All of the Small Cell RFSDK cases, use these stream rates.

    4Tx, 4Rx streams - matches existing RFSDK 4 stream case
    serdes rate, 4.9152Gbps
    DFEclk 245.76
    BB rate - 30.72e6
    Tx DDUC In 30.72e6, out 30.72e6
    Tx stream rate before CFR - 30.72e6
    Tx stream rate after CFR - 61.44e6
    Tx stream rate before DPD - 122.88e6
    Observation receiver if DPD is used 122.88e6

    Rx stream input 61.44e6
    Rx stream output after Rx block 30.72e6
    Rx DDUC in 30.72e6, out 30.72e6
    BB rate - 30.72e6

    serdes rate, 7.3728Gbps
    DFEclk 368.64e6
    Tx DDUC In 30.72e6, out 46.08e6
    Tx stream rate before CFR - 46.08e6
    Tx stream rate after CFR - 92.16e6
    Tx stream rate before DPD - 184.32e6
    Observation receiver if DPD is used 184.32e6

    Rx stream input 92.16e6
    Rx stream output after Rx block 46.08e6
    Rx DDUC in 46.08e6e6, out 30.72e6
    BB rate - 30.72e6

    Regards,
    Joe Quintal
  • Hi Joe,

    Thanks for the information.

    This info is really helpful.

    Regards,

    Sumathi

  • Hi Joe,

    Thank You for the support. Have updated the DFE BB data rates in the attached block diagram. Kindly let me know whether it is OK.

    Regarding the TX data stream value 4.9152Gbps kindly let me know whether the calculation is OK.

    With DFE clock of 245.76MHz,

    The TX data rate at JESD Interface is 

    =245.76MHz x 16 x 10/8 = 4.915Gbps, is this way of calculation correct?

    Total serial data rate for 4 TX lanes with complex inputs is

    ==4.915 x 2 x 4 = 39.321GBps

    ----------------------------------------------------------------------------------------------------

    The RX data rate at JESD Interface is half the TX rate. But DFE Clock is 245.76MHz, so kindly let me know how to get 61.44e6?

    Do we have to consider 245.76MHz / 2 ?? that is 122.88MHz for RX. The SYSCLK for JESD interface is same as DFE clock

    --------------------------------------------------------------------------------------------------------------------------------------------------------------------

    On the RF side , AFE7500 or AFE7xxx 4Tx4R, we want to operate on band 40 LTE TDD Frequency 2300 to 2400 MHz with bandwidth of 20MHz..

    The NCO must be set to 2350MHz on AFE7xxx, for carrier frequency, is it correct?

    The JESD data rate 39.321GBps (4 TX) is modulated with carrier of 2350MHz for transmission at the output of PA. 

    Would like to understand the complete path from DFE - IQN2 BB data rate to AFE7xxx output. Kindly let me know whether my understanding is correct.

    The AFE7xxx ADC and DAC LMFSHd settings is required for 4T x 4R..Configuration

    Kindly reply..

    Regards,

    Sumathi

  • Hello,

    The interface from DFE to the serdes is 16bit parallel per serdes.   The serdes are operated in pairs, JESD0,1 (shared with AIL), and JESD2,3.

    The JESD standard using 8B/10B coding, 

    The serdes line rate must be the same between the Tx and Rx side of the serdes in a pair.

    Related to 4 Tx, 4Rx - there is already a working example in the RFSDK,  (search for RFSDK on TI website, you can request and download Linux software)

    The Integrated Transceiver supported is the AFE7500.

    In the case of 4 Tx, each Tx uses one lane in Interleaved IQ (F=4) format.   122.88Msps stream rate * (F/2) * 20bits/sample = 4.9152Gbps

    Digital PreDistortion uses the Observation receiver has 1 Rx lane from each of 2 integrated transceivers.  This uses internal switching inside DFE

    to select which transceiver is being selected.  Inside the Integrated transceiver, there is a selector from 1 of 2 observation paths.

    The receive is processed as 2 interleaved IQ streams (F=8) per Receive lane, one from each Integrated Transceiver.

    61.44Msps stream rate * (F/2) * 20bits/sample = 4.9152Gbps.

    Internal to DFE there is special gating logic to manage stream to DFEclock rates, this is not user adjustable, it is part of the configuration.

    When you download the RFSDK there is a user and installation guide, that has more information on the available 4x4...... configurations.

    Regards,

    Joe Quintal

     

  • Hello Joe,

    Thanks for the support.

    The SYSCLK for K2L we are applying is 122.88MHz. Is this fine for generating DFE CLOCK of 245.76MHz ???

    We are using two clock devices CDCM6208 and LMK04828.

    The CDCM6208 is used to generate K2L clocks like SYSCLK, SGMII Clock, DDR3, PCIe, USB,etc

    The LMK04828 is used to generate, SYSREF for K2L. FMC connector SYSCLK and SYSREF.

    One clock output from CDCM6208 is used as reference input to LMK04828. So that CDCM6208 and LM04828 are in Sync .. IS this ok?

    Means the SYSCLK is generated by CDCM6208 and SYSREF is generated by LMK04828.

    Kindly reply..

    Regards,

    Sumathi

  • Hi Joe,
    Just one more point to consider here is, we are using 2 Antennas.
    So per antenna it is 2 TX and 2 RX. There fore for 2 Antenna overall, 4 TX and 4RX.
    In this case what is the IQ interleave factor " F" for TX and RX.

    Regards,
    Sumathi
  • Hello,

    The clock distribution for DFE, JESD204, and Serdes are that they all use 122.88Mhz clocks.

    SYSREF is a divided version of the 122.88Mhz clock / n

    SYSREF needs to be distributed to the JESD204 devices, it normally uses a 122.88Mhz clock.

    Internally DFE takes the routed SOC 122.88Mhz clock, and develops the 245.76 or 368.64Mhz clocks (also for IQNet/AIL).

    The Serdes also need the 122.88Mhz clocks.

    REgards,

    Joe Quintal

  • Hello,
    In the consideration of using 2 vs 4 antennas you have a choice of parallel IQ (two lanes per antenna, F=2) or interleaved IQ (one lane per antenna, F=4). The Integrated transceivers for the Rx path share Rx with the observation path, so in some cases, the Rx is a different format:

    example a - two antenna, two JESD lane, with observation receiver
    (2lane) Tx - two antenna interleaved IQ F=4, 122.88Mhz
    (1lane) Rx - two antenna interleaved IQ F=8, 61.44Mhz
    (1lane) observation - interleaved IQ F=4, 122.88MHz

    example a - two antenna, two JESD lane, no observation receiver
    (2lane) Tx - two antenna interleaved IQ F=4, 122.88Mhz
    (2lane) Rx - two interleaved IQ F=4, 122.88Mhz

    example a - two antenna, four JESD lane, with observation receiver
    (4lane) Tx - two antenna parallel IQ F=2, 245.76Mhz
    (2lane) Rx - two antenna interleaved IQ F=4, 122.88Mhz
    (2lane) observation - parallel IQ F=2, 245.76MHz

    example a - two antenna, four JESD lane, no observation receiver
    (4lane) Tx - two antenna parallel IQ F=2, 245.76Mhz
    (4lane) Rx - two antenna parallel IQ F=2, 245.76Mhz

    Please see more details in the TCI6630K2L/66aK2L06 - DFE User Guide

    Regards,
    Joe Quintal
  • Hello Joe,
    Thank You very much for the excellent support. Its really kind of you for the immediate reply. Could you please share your official email -id. Would like to send you the design schematics for final review. We have to complete the testing by this November end. production scheduled for 2019 Q1. Kindly reply..

    Regards,
    Sumathi
  • Hello Joe,
    I have few more query.
    I have downloaded RFSDK, but I was not able to install on windows. So will try to install in ubuntu.
    regarding the DFE GPIO's. Is there any specific GPIO number that need to be interfaced to FMC connector? can we connect any DFE GPIO in any order. basically I would like to know if there is specific DFE GPIO numbering for TX RX PA control and configuration. Else they must be changed in the SW which may be difficult.
    In RFSDK, which are the files that we need to look into for the AFE500 initial configuration and bring up.
    Actually, In our Board, we have a FMC connector, For which we are providing option that can be interfaced to AFE7500 (2Tx2R) or AFE7XXX for (4Tx4R).

    The number of antenna we will be using is 2 antennas.

    Regards,
    Sumathi
  • Hello,

    The DFE GPIOs are remapped through the FPGA on the TCI6630K2L/66AK2l06 EVM.   You need to follow the EVM schematic, and then the attached FPGA source code.  

    The DFE GPIOs can be System peripheral pins (please check if TDD is used, they are modified for this, they are not generic).  The same pins can be System GPIOs, or DFE functions (see DFE user Guide), or DFE GPIOs.

    The Small Cell use cases are listed in the RFSDK Radio Select - look in the RFSDK User Guide.

    2 lane - 2 stream, (2)122.88Mhz Tx, (2)1lane, 61.44Mhz Rx, (1)1lane, 122.88Mhz Observation, JESD01, 4.9152Gbps

    4 lane - 4 stream, (4)122.88Mhz Tx, (4)2lane, 61.44Mhz Rx,  (2)2lane, 122.88Mhz Observation, JESD0123, 4.9152Gbps

    note: different Integrated Transceiver EVM revisions are needed to support  use on both FMC connectors to the TI EVM.

    EVM FPGA source code including TDD for AFE7500 -

    If you want to have a review, this needs to go through your local TI Field Application Engineer or Technical Sales Representative, or Distributor

    Engineering.   They can setup the internal TI email bridge.

    Regards,

    Joe Quintal

    8054.ti_evm_k2l_4C_TDD.zip

  • Once you have installed the RFSDK, in the Linux environment, you will need to work with the Integrated Transceiver software team.
    The board file, indicates which data converters are used. The RFSDK python to C to SPI source code is provided. The afe7500 commands have corresponding references to the SPI commands. If you have a different integrated transceiver, you will need to add a board type, and the equivalent additional commands for that device.
    This is considered RFSDK customization, which is only supported through 3rd parties, Comm Agility, and Azcom.
    Regards,
    Joe Quintal
  • Hi Joe,

    Thanks again for providing us an excellent support.

    We are designing the LTE enodeB based on the K2L EVM. But the only difference is we are not using FPGA and we are using TIVA tm4c1294ncpdt as BMC controller.

    This design has only one FMC connector interface. The FMC is used to interface AFE7500 for 2T x 2R (OR) AFE7xxx for 4T x 4R via the 4 JESD lanes from SOC.

    All the AFE configuration is taken care by the processor (K2L) via SPI and DFE GPIO..

    So In this design we are not using FPGA.

    Regards,

    Sumathi

  • Hi Joe,
    I had one more query regarding the K2L clocks. Kindly confirm whether this is ok.
    We are using CDCM6208 to generate SYSCLK and all other clocks related to K2L like, DDR3 clock, SGMII, Altcore clock, USB PCIe etc. We are using LMK04828 to generate SYSREF for K2L, DEVCLK and SYSREF for FMC connector for AFE7500 and AFE7xxx interface. One clock output from CDCM6208 is used as reference input to LMK04828 for Sync between the two Clock generators. Kindly confirm whether this is OK.
    Kindly reply,
    Regards,
    Sumathi
  • Hi Joe,
    We are using SN74CB3Q16210DGVR in our design. The Data I/O signal are 1.8V ( DFE of TCI6630K2LXCMSA2 Processor) that are to be switched. ""The Data I/Os Support 0 V to 5 V Signaling
    Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V,5 V)"" from the datasheet. The VCC is in the range of 2.5 to 3.3V
    Therefore for 1.8V signals, do we need to connect 1.8V to the Power VCC pin or 3.3V??
    Kindly reply,
    Regards,
    Sumathi
  • Hello,
    You need to use a switch that allows for a 1.8v input on the K2L side, and a 3.3v on the external side. You need to check on the speed of the signals needed, to select a switch. If there are current drive requirements, that also needs to be considered.
    The device datasheet should allow for 1.8v on the K2L power side.

    Regards,
    Joe Quintal
  • Hello,
    Please look at the FPGA data sent. If TDD is used for AFE7500 controls, you will need to change the internal SOC timers and logic to generate the signals for AFE7500. This is further discussed in the RFSDK User Guide.

    While you may not need SPI or GPIO expansion, the TDD generator should be retained, if you don't want to redesign this control section.

    Regards,
    Joe Quintal
  • Thanks a lot Joe,

    Regards,

    Sumathi