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AM5716: problems w/ GEL file conversion

Part Number: AM5716

hi,

a customer of mine is trying to port our SW to their customized board.

They tried the SBL project and the GEL file conversions, but they faced some challenges. 

Do you have an example project for the AM5716D 500 MHz?

thanks a lot in advance

KR

Vincenzo

  • KR,

    We need more information than "faced some challenges". Do you have a build log or more specifics on what is the issue with SBL and what is the issue using the GEL files. Is it clocking related or DDR related or pinmux related or something else. We would appreciate if you can provide this detail.

    For AM571x running at lower clocks has been described here:
    processors.wiki.ti.com/.../AM570x_Speed_Grades

    Is the customer using the above document for the setup. What are the differences between customer board and TI AM571x IDK other than the lower speed grade variant?

    Have they referred to the porting section of the Processor SDK RTOS training and used the tools that we provide to help with this porting?
    software-dl.ti.com/.../presentation_html5.html (Section 9)

    Hope this helps you provide some guidance to your customer and also provide us more information to analyze the issue.

    Regards,
    Rahul
  • hi Rahul,

    thanks a lot for the prompt reply...

    1 . We have made a U-boot package, customized for our board, but this MLO version did not start from SD card. We see the communication signals in oscilloscope, but we did not see any communication from UART.

    2. We try to debug this with the XDS110 JTAGE debug probe(we used the TI U-boot Debug in CCS manual), but from some steps the PC enter in 0x0000000c address and it stops there.

    Now, we try the TI RTOS SBL porting to our board, we want to test the peripherals step by step.

    does this narrow down the potential root causes?
    thanks a lot in advance
    KR
    Vincenzo
  • Vincenzo,

    While the above provides context for why the customer is trying to use GEL and SBL, it doesn`t indicate what problem they ran into:

    Have they setup JTAG and the board as described here:
    processors.wiki.ti.com/.../TMDXIDK5728_Hardware_Setup
    processors.wiki.ti.com/.../AM572x_GP_EVM_Hardware_Setup

    they need to make sure DDR configuration and clocking in the GEL files is modified for their board or try this on TI Evaluation platform before testing on their own board. Once this is up and running, they need to update the pinmux setup, DDR and clocks in the board library and build diagnostics package:

    Refer Section 9 Board porting guide : software-dl.ti.com/.../presentation_html5.html

    Diagnostics:
    software-dl.ti.com/.../Board_EVM_Abstration.html

    Running DDR, UART, flash and ethernet PHY test should be a good point to confirm basic board level functionality.

    Final step would be to switch to the Linux setup:

    Linux Board porting: https://training.ti.com/linux-board-porting-series-module-4-linuxu-boot-source-code-structure 

    Regards,
    Rahul

  • hi Rahul,

    We made the board port using the above mentioned documentation, but we have a doubt.

    In this documentation the DDR3 speed is 1330 MHz, but in processor datasheet the DDR3 speed is 1066 MHz.

    Which one is the correct speed? 

    http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/How_to_Guides.html#processor-sdk-rtos-porting-guide-for-am571x-am570x-speed-grades

    Another question raised in the meantime:

    How we can generate <board>_pinmux.c  files?

    We found that this file can be generated by pinmux tool, but the actual cloud version does not contain starterware filter .

     

    Thanks a lot in advance

    KR

    Vincenzo

  • Vincenzo,

    I would follow the datasheet guidelines for max DDR speed supported on the SOC. Are you looking at the AM5716 data sheet or AM572x ? I have attached a screenshot that confirms the 1333 support:

    Vincenzo Pizzolante said:

    How we can generate <board>_pinmux.c  files?

    We found that this file can be generated by pinmux tool, but the actual cloud version does not contain starterware filter .

    Can you confirm that you are using Processor SDK RTOS for AM57xx devices when you refer to board library ? Why do you need starterware filter? We don`t have any starterware component for these devices so make sure that you are using the correct software package.

    For AM57xx devices, the files should be direct drop in replacement in the board library as shown in section 9.5 of the training here:

    http://software-dl.ti.com/public/hpmp/software/app_dev_procsdk_rtos/presentation_html5.html

    Regards,

    Rahul

  • hi Rahul,

    We are using the AM5716D device, and we found two conflicting information about the maximum frequency of the DDR3 memory.

    In the RTOS documentation porting guide:

    And in the AM571x Data sheet:

    We insisted on the datasheet, and wait for a verification.

    The other question details:

    I'm using the PROCESSOR-SDK-RTOS-AM57X  05_01_00_15, and I follow the porting guide part of the documentation step by step. (http://software-dl.ti.com/processor-sdk-rtos/esd/docs/05_01_00_11/rtos/How_to_Guides.html#adding-custom-board-library-target-to-processor-sdk-rtos-makefiles)

    In the first step I copied and renamed the files from the idkAM571x directory (<home>/ti_psdk/pdk_am57xx_1_0_11/packages/ti/board/src/idkAM571x) to the new cc17 directory.

    Then I replaced the BoardPadDelay* files with the PinMux tool generated ones.

    I made a Code Composer Studio project for the SBL, to test the new board library, following this guide: http://processors.wiki.ti.com/index.php/Creating_a_CCS_Project_for_SBL_on_AM572x_GP_EVM

    In sbl_main.c I inserted a code snippet to validate the HW design and SW environment: it should light on a LED connected to the Port1-26, but it didn't work, until I changed the code in the cc17_ pinmux.c (it was idkAM571x_pinmux.c originally), in the PinmuxGpioLedConfig() function from

        CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_CS0_GPMC_CS0_MUXMODE, 0xEU);
        ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPMC_CS0 = regVal;

    to

        CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_GPMC_A4_GPMC_A4_MUXMODE, 0xEU);
        ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPMC_A4 = regVal;

    and the LED started blinking. After that I changed  int the PinmuxUartConfig() function

         case 3:
                regVal = 0U;
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_RTSN_UART2_RTSN_WAKEUPENABLE, DISABLE);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_RTSN_UART2_RTSN_SLEWCONTROL, SLOW_SLEW);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_RTSN_UART2_RTSN_INPUTENABLE, ENABLE);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_RTSN_UART2_RTSN_PULLTYPESELECT, PULL_UP);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_RTSN_UART2_RTSN_PULLUDENABLE, DISABLE);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_RTSN_UART2_RTSN_MODESELECT, MUX_MODE);
                CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_RTSN_UART2_RTSN_DELAYMODE, 0U);
                CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_RTSN_UART2_RTSN_MUXMODE, 1U);
                ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_UART2_RTSN = regVal;

                regVal = 0U;
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_CTSN_UART2_CTSN_WAKEUPENABLE, DISABLE);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_CTSN_UART2_CTSN_SLEWCONTROL, SLOW_SLEW);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_CTSN_UART2_CTSN_INPUTENABLE, ENABLE);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_CTSN_UART2_CTSN_PULLTYPESELECT, PULL_UP);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_CTSN_UART2_CTSN_PULLUDENABLE, DISABLE);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_CTSN_UART2_CTSN_MODESELECT, MUX_MODE);
                CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_CTSN_UART2_CTSN_DELAYMODE, 0U);
                CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART2_CTSN_UART2_CTSN_MUXMODE, 2U);
                ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_UART2_CTSN = regVal;
                break;

    lines to

       case 3:
                regVal = 0U;
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_RXD_UART3_RXD_WAKEUPENABLE, DISABLE);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_RXD_UART3_RXD_SLEWCONTROL, SLOW_SLEW);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_RXD_UART3_RXD_INPUTENABLE, ENABLE);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_RXD_UART3_RXD_PULLTYPESELECT, PULL_UP);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_RXD_UART3_RXD_PULLUDENABLE, DISABLE);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_RXD_UART3_RXD_MODESELECT, MUX_MODE);
                CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_RXD_UART3_RXD_DELAYMODE, 0U);
                CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_RXD_UART3_RXD_MUXMODE, 0U);
                ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_UART3_RXD = regVal;

                regVal = 0U;
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_TXD_UART3_TXD_WAKEUPENABLE, DISABLE);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_TXD_UART3_TXD_SLEWCONTROL, SLOW_SLEW);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_TXD_UART3_TXD_INPUTENABLE, DISABLE);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_TXD_UART3_TXD_PULLTYPESELECT, PULL_UP);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_TXD_UART3_TXD_PULLUDENABLE, DISABLE);
                CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_TXD_UART3_TXD_MODESELECT, MUX_MODE);
                CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_TXD_UART3_TXD_DELAYMODE, 0U);
                CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_UART3_TXD_UART3_TXD_MUXMODE, 0U);
                ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_UART3_TXD = regVal;
                break;

     

    and the UART3 started to work as a standard output. But it seems inconvenient to try and guess all necessity changes for all the used peripheries. 

    Maybe there is an easier way to accomplish the HW differences of our customized board?

    And one new question: what about the cc17_ddr3.c / idk571x_ddr3.c files?

    The EMIF tool only generate files in GEL and U-BOOT conformable format, it looks that is different that the board library ones.

    thanks a lot in advance

    KR

    Vincenzo

     

  • Vincenzo, 

    Thank you for bringing the mismatch in spec in SW documentation and DM collateral. We are following up with the marketting and documentation team on what caused the change in DDR spec for the 500 Mhz variant and we will get back to you on this issue. 

    As far as the EMIF tool is concerned. the intended use for board library users is to first generated the DDR config output for the GEL file and validate using GEL and then port the code over to board library. The board library code follows the GEL code closely. 

    As far as updating pinmux in the board library, we don`t recommend doing this manually. We have a pinmux tool that generates the board library files for configuring the pins.  I highly recommmend that you refer to the section 9.5 in the training here: http://software-dl.ti.com/public/hpmp/software/app_dev_procsdk_rtos/presentation_html5.html

    TI Pinmux tool : http://www.ti.com/tool/PINMUXTOOL 

    Regards,

    Rahul

  • thnaks a lot Rahul,

    a very last question (and then I can close the thread).

    may you point me our to any documentation (if exists), about how to port the validated GEL code over to board library?

    thansk a lot in advance

    KR

    Vincenzo

  • All of the DDR configuration functions in the board library are in the file pdk_am57xx_1_0_11\packages\ti\board\src\idkAM572x\idkAM572x_ddr.c for IDK platform.

    If you open the GeL file AM571x_ddr_config.gel in the folder C:\ti\ccsv8\ccs_base\emulation\boards\am571x\gel, locate the configuration function AM571x_DDR3_666MHz_Config, this shows the sequence in which DDR needs to configured. It appears as follow:

    /* DDR PLL config */
    dpll_ddr_config(666); //set DDR PLL
    AM571x_CM_DDRIO_Config(); // set DDRIO
    AM571x_reset_emif_params_ddr3_666(SOC_EMIF1_CONF_REGS_BASE); //Reset

    AM571x_set_emif1_params_ddr3_666(SOC_EMIF1_CONF_REGS_BASE); // setup DDR timing
    EMIF_Config(SOC_EMIF1_CONF_REGS_BASE, HW_LEVELING_ENABLED,ENABLE_ECC); // Apply the configuration
    AM571x_set_lisa_maps(); //set LISA maps

    The same setting in board library is done using Board_DDR3Init, line 102 ro line 190 is same as DDRIO config and setting DDR timings. EMIF_config function maps to emifConfigureDdr3 and line 194 to 207 is setting up of LISA map. The DDR PLL is set as part of Board_PLLInit in the file idkAM571x_pll which you don`t need to update if you are not changing the clocking.

    Hope this provides some insight into the porting effort.

    Regards,
    Rahul