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AM3352: wait time for DDR3

Part Number: AM3352

Hi Sitara Support Team,

Regarding DDR3 operation, is there any information for the wait time from register setting to using DDR3?

[Background]*****************************************************************
-Depending on the DDR size and the cpu speed on the same board,
  there are differences operating as follows.

<Board #1: Operating OK>
・AM3352 300MHz with DDR3: 303MHz
・samsung: K4B1G1646E-BYK0(size:1Gb)

<Board #2: Operating NG>
・AM3352 600MHz with DDR3: 303MHz
・samsung: K4B4G1646E-BYK0(size:4Gb)

<Board #2 + Adding 350us wait time: Operating OK>
・AM3352 600MHz with DDR3: 303MHz
・samsung: K4B4G1646E-BYK0(size:4Gb)

[Register setting]
-SDRAM_CONFIG         :0x61C05232 //size:1G
-SDRAM_CONFIG         :0x61C05332 //size:4G
-SDRAM_REF_CTRL :0x93B
-DDR_IO_CTRL            :0x00000000
-VTP_CTRL *controlled it as the AM335x EMIF Configuration tips site
-VREF_CTRL                :0x00000000
-DDR_CKE_CTRL         :1
-DDR_CMD0_IOCTRL/ DDR_CMD1_IOCTRL/ DDR_CMD2_IOCTRL   :0x0000018B
-DDR_DATA0_IOCTRL/ DDR_DATA1_IOCTRL                  :0x0000018B
-DATA_PHY_RD_DQS_SLAVE_RATIO   :0x3a
-DATA_PHY_FIFO_WE_SLAVE_RATIO  :0x9a
-DATA_PHY_WR_DQS_SLAVE_RATIO  :0x3c
-DATA_PHY_WR_DATA_SLAVE_RATIO :0x75

[Other setting data]
-SDRAM_TIMING1 :0x0888B3DB
-SDRAM_TIMING2 :0x2A517FDA
-SDRAM_TIMING3 :0x501F84EF
-READ_LATENCY  :0x07

-ZQ_CONFIG          :0x50074BE4 

*******************************************************************************

Best regards,
Kanae

  • Kanae, it is not clear where exactly are they putting the 350us delay.  Is it somewhere in the initialization sequence?  After initialization?  Somewhere else?

    Regards,

    james

  • Hi james,

    Thank you for your reply.

    They are putting the 350us delay to u-boot source; board/ti/am335x/board.c
    as follows.


    void sdram_init(void)
    {
    config_ddr(303, &ddr_ioregs, &ddr3_data,
    &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);

    udelay(350); <---Adding
    }


    The 350us wait was added simply after the register setting (config_ddr function).
    The code is different from the SDKv5 itself, since the setting for each board is deleted from SDK.
    However it is not deleted some wait processing from the SDKv5.

    Best regards,
    Kanae

  • Kanae, i'm not sure what you mean by "The code is different from the SDKv5 itself, since the setting for each board is deleted from SDK.". Because a delay seems to be needed, your customer may have a power ramp issue. Can he check to see if his power supplies are ramped and stable before the config_ddr function is called? Can they also try to reset the board (keep power alive) and see if the delay is necessary. Be sure to check all supplies, including VREF and VTT (if applicable)

    Regards,
    James
  • Hi James,

    Thank you for your support.

    "The code is different from the SDKv5 itself" means
    that they have just remove the setting of some evm such as
    GP EVM, SK, ICEv2 from "void sdram_init(void)" in SDK.


    Here is the result of my customer's confirmation.

    ***********************************************************
    It was NG when adding only ① in the following source code.
    It was OK when adding only ② in the following source code.

    void sdram_init (void)
    {
    udelay (350); ① <--- Even if adding time to 1 ms
    Config_ddr (303, & ddr_ioregs, & ddr3_data,
    & ddr3_cmd_ctrl_data, & ddr3_emif_reg_data, 0);

    udelay (350); ② <--- add
    }


    Based on this fact, we have judged that it is no problem you concerned.
    Therefore, we suppose that it needs the wait time
    from the register setting to using it.
    *************************************************************

    Is their understanding / their solution correct?

    Best regards,
    Kanae

  • Kanae, the delay after config_ddr should not be necessary. There is something else going on which I'm not able to understand. Are they using the same DDR configuration register settings between the working 1Gb device and the non working 4Gb device

    Regards,
    James
  • Hi James,

    Thank you for your reply.

    Regarding DDR configuration register, the timing is same the both 1G: DDR3 and 4G: DDR3.
    SDRAM CONFIG registers are different as I posted.
    The part of row address size is not same.

    -SDRAM_CONFIG         :0x61C05232 //size:1G
    -SDRAM_CONFIG         :0x61C05332 //size:4G

    If you have any other concerns, please let me know.

    Best regards,
    Kanae

  • Sorry Kanae, I was mainly referring to the SDRAM_TIMINGx registers. These will be different for each device since they are different densities. Particularly, tRFC, and those parameters that are dependent on tRFC, will be different. Do they have different configuration for each memory/

    Regards,
    james
  • Hi James,

    Thank you for your reply.

    My customer was making a mistake report.
    The correct settings are as follows.


    DDR3                                    4G    1G

    SDRAM_CONFIG                  0x61C05332 0x61C05232

    DATA_PHY_RD_DQS_SLAVE_RATIO   0x3a   0x33
    DATA_PHY_FIFO_WE_SLAVE_RATIO  0x9a      0c9b
    DATA_PHY_WR_DQS_SLAVE_RATIO  0x3c    0x39
    DATA_PHY_WR_DATA_SLAVE_RATIO 0x75   0x73

    SDRAM_TIMING1              0x0888B3DB     0x0888B3DB
    SDRAM_TIMING2              0x2A517FDA  0x2A242FDA
    SDRAM_TIMING3              0x501F84EF   0x501F821F


    The board using "4Gb DDR3" with the above setting has error,
    but the board using "1Gb DDR3" does not have any error.

    Do you think that customer should not add the wait time for this error?
    Should they adjust these parameters for "4Gb DDR3" board?

    Best regards,
    Kanae

  • Hi James,

    I would like to confirm the value of "ODTLon" in AM335x_DDR_register_calc_tool.
    The value should be "3" in "ODTLon", if the DDR's CWL value is "5" and AL is "0".
    Is it correct?
    I refer the following thread.
    e2e.ti.com/.../2434222

    Best regards,
    Kanae

  • Hi James,

    The "ODTLon" value is set "3" instead of "5",
    since the DDR's CWL value is "5" and AL is "0".

    However the board using "4Gb DDR3" with the above setting has error,
    Is my understanding "ODTLon = CWL + AL - 2" correct as sivak posted in this thread?

    Or, the latest AM335x TRM does not show "REG_T_ODT[27:25]" of SDRAM_TIM_2 register.
    "REG_T_ODT[27:25]" of SDRAM_TIM_2 register is changed to "RESERVED".
    So, should the value in bit [27:25] of SDRAM_TIM_2 register set "2"?

    Best regards,
    Kanae

  • Kanae, Bits 27-25 are only applicable when DLL is off. This mode is not valid with AM335x, so those bits are irrelevant and not used, so they should be left as default 0x2.

    thanks,
    James
  • Hi James,

    Thank you for your reply.
    My customer changed the bit from "5"; in config tool, to "2"; default value.
    However it unfortunately is no effect.

    I would like to know the parameter of DDR3.
    The current setting is used "the value of DDR3-800" in K4B4G1646E-BYK0 datasheet.
    Because the customer board setting is 600MHz with DDR3: 303MHz.
    But I found the this thread for C6678.

    e2e.ti.com/.../2714583

    Can we refer this for AM335x DDR3 setting?
    My customer uses "K4B4G1646E-BYK0" that is "DDR3L-1600" in a datasheet.
    So does they take "the value of DDR3-1600" in K4B4G1646E-BYK0 datasheet
    in stead of "the value of DDR3-800"?

    Best regards,
    Kanae
  • Kanae, the guidance in thread you point to is correct. Your customer should be using the datasheet parameters associated with the speed grade of the device, which in their case is DDR3-1600. In the speed bin table DDR3-1600, they should be using the CL and CWL parameters associated with the operational speed (ie. 400MHz, or 2.5ns) of the device.

    Regards,
    James
  • Hi James,

    Thank you for your reply.

    I would like to make sure the using parameters.
    Should customer use the following highlighted parameters?
    When the operating speed is "3.3ns", can they set "3.3ns" to "tCK"
    in the DDR_register_calc_tool?

    Best regards,
    Kanae

  • Yes, when operating at 303MHz (3.3ns cycle time), they should set tCK in the tool to 3.3ns, and use the highlighted values as you have shown.

    Regards,
    James