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66AK2G12: Question about manipulating QSPI_BasicExample_evmK2G_armTestProject

Part Number: 66AK2G12

Hi guys, 

My customer has the below question:

pdk_k2g_1_0_7

bios : 6.46.5.55

xdctools_3_32_01_22_core

 

I built a QSPI test SW based on QSPI_BasicExample_evmK2G_armTestProject to test my board. My QSPI component is the same as the QSPI on K2G EVM.

 

My test code uses three QSPI APIs: Board_flashEraseBlk, Board_flashWrite and Board_flashRead as followed in a infinite loop

 

    ioMode = BOARD_FLASH_QSPI_IO_MODE_QUAD;

              

    while(1)

    {

        Semaphore_pend(semQspi, BIOS_WAIT_FOREVER);

                             

        /* Erase block, to which data has to be written */

        if (Board_flashEraseBlk(boardHandle, blockNum))

        {

            SPI_log("\n Board_flashEraseBlk failed. \n");

            testPassed = false;

            break;

        }

 

        /* Generate the data */

        GeneratePattern(txBuf, rxBuf, TEST_DATA_LEN);

 

        /* Write buffer to flash */

        if (Board_flashWrite(boardHandle, TEST_ADDR_OFFSET, txBuf,

                             TEST_DATA_LEN, (void *)(&ioMode)))

        {

            SPI_log("\n Board_flashWrite failed. \n");

            testPassed = false;

            break;

        }

 

        /* Reset receive buffer */

        if (Board_flashRead(boardHandle, TEST_ADDR_OFFSET, rxBuf,

                            TEST_DATA_LEN, (void *)(&ioMode)))

        {

            SPI_log("\n Board_flashRead failed. \n");

            testPassed = false;

            break;

        }

 

        /* Verify Data */

        if (VerifyData(txBuf, rxBuf, TEST_DATA_LEN) == false)

        {

            SPI_log("\n Data mismatch. \n");

            testPassed = false;

            break;

        }

 

    }

 

The semaphore, Qspi, is posted every second by a clock module. So, the loop is running every second. I have tried to run every 3 seconds and still got the same issue.

My test is always stalled in Board_flashRead API after several minutes testing. I insert code to toggle GPIO pins in several places to identify the place where the code is stalled.

and found it is waiting a word completion interrupt to post a semaphore forever.

 

In C:\ti\pdk_k2g_1_0_7\packages\ti\drv\spi\src\v0\QSPI_v0.clock

Line 884

                if (object->qspiMode == QSPI_OPER_MODE_IND_XFER)

                {

                    /* Only in indirect transfer mode, wait for the lock

                       posted form the word completion interrupt */

                    SPI_osalPendLock(object->transferComplete, SemaphoreP_WAIT_FOREVER);

                }           

 

                                                           

The issue is gone if I change ioMode

from

ioMode = BOARD_FLASH_QSPI_IO_MODE_QUAD;

to

ioMode = BOARD_FLASH_QSPI_IO_MODE_SINGLE;

 

Q1: How is the word completion interrupt generated? How to identify it from probing QSPI signal lines?

Q2: Can the issue be resolves if I change SemaphoreP_WAIT_FOREVER to a limited time and recall Board_flashRead API if it returns error. I am not sure if I need to check/clean interrupts or additional stuff before call Board_flashRead again if it fails previously.

Thanks,

Brian

  • Brian,

    Is the test being performed for testing QSPI flash robustness? I am not sure what is going on as the issue seems to go away in single pin mode.

    Do you know at what speed the read writes are happening? Is this at default 1 MHz or have you changed the speed.

    It does appear that a time out would have helped in this case to exit out of the error condition. Is it possible to post the updated test code here so we can try to reproduce the issue at our end.

    Regards,
    Rahul
  • Rahul,

    The test is for testing robustness of layout and QSPI flash.
    The speed for both read and write is 12MHz. The QSPI flash supports 50MHz. Does QSPI driver support 12MHz?
    I will test with default 1MHz. If I still get the same issue I will let you try my test code. Thanks.

    Regards,
    Brian
  • Rahul,

    They haven’t tested it with 1MHz yet since they changed the following code but still got QSPI_SCK at 12MHz.

    /* Set default baud rate divider value */
    // QSPISetPreScaler(QSPI_CONFIG_REG, QSPI_BAUD_RATE_DIVISOR_DEFAULT); // 15=(192MHz/12MHz)-1
    QSPISetPreScaler(QSPI_CONFIG_REG, 191); // (192MHz/1MHz)-1

    How do they set QSPI_SCK to 1MHz?

    Does QSPI driver support 12MHz?

    In addition here is a scope capture of their QSPI_CLK at 12MHz attempt:


    Ch1, in yellow, is a GPIO pin. It is set to HIGH when QSPI API Board_flashRead is running.

    Ch2, in blue, is QSPI_D2 signal.

    Ch3, in pink, is QSPI_CLK.

    Ch4, in green, is QSPI_D3.

     

    The GPIO doesn’t return to LOW since API Board_flashRead is stalled.

    Board_flashWrite Is running before Board_flashRead. From captured waveform the QSPI flash returns the data was written before . The cause of READ stalled should be on K2G side.

    Thanks,
    Brian

  • How do they set QSPI_SCK to 1MHz?

    Does QSPI driver support 12MHz?

    Thanks,
    Brian
  • Brian,

    Sorry, I thought that I had responded to this email. Yes, QSPI driver supports 12 Mhz Quad mode which seems to be the default setting and is also used by the bootloader and the flash writer.

    QSPI clock is obtained from UART PLL on K2G which runs at 384 Mhz and the baud rate prescalar is set to 32 which results in the 12 MHz clock. That is the max value of the divider so it may not be possible to get to 1 Mhz without lowering the UART PLL which has implication on the UART baudrate setting. The configuration of the clock is done in the driver using the following code:

    In QSPI driver QSPI_v0.c, you will find the baud rate setting. UART PLL is set in the board library and in the GEL files

    /* Set default baud rate divider value */
    QSPISetPreScaler(hwAttrs->baseAddr, QSPI_BAUD_RATE_DIVISOR_DEFAULT);

    The QSPI_BAUD_RATE_DIVISOR_DEFAULT is set from the CSL file, pdk_k2g_1_0_10\packages\ti\csl\src\ip\qspi\V0\qspi.h

    At this point the path of least resistance to move forward would be to provide the source code to allow us to reproduce this issue on the K2G EVM. Is this something that you can provide?

    Regards,
    Rahul