66AK2G12: Questions about DDR3 register calc tool

NK,

See below:

1. They will use MT41K64M16TW107AIT(DDR3L-1866) with the clock of 666.666 Mhz (1333MT/s). In this case, they will have to set C9 cell to "User defined" and take the required TIMING values from the datacheet to fill out SDRAM Timing Values in the Design Parameter sheet. Correct?

TI: Yes, this is correct. You will pull the timing values from the 1866 speed bin tables but you must select the appropriate values based on the 1333MT/s data rate (such as CL). Note that you should select the values using the slowest memory that will be installed – such as DDR3L-1600 SDRAMs.

2. In the Refresh Configuration table in the Design Parameter sheet, what value should be set in INITREF_DIS? I believe it should be basically set to "Normal Operation", but they have another option "Disable SDRAM Initialization and Refresh". Could you please explain the use case for this?

TI: This selection maps to the MSB in the SDRFC register that enables or disables the initialization during Controller register accesses. For the purposes of this spreadsheet, this bit will always be enabled. You can see this used in section 3.5.4 of the Keystone II DDR3 Initialization Application Report (SPRABX7). More information about the use of this bit is shown in section 2.11.1 of the Keystone II Architecture DDR3 Memory Controller User's Guide (SPRUHN7C).

3. In the Controller Register sheet, there is a bit field "T_RTW " in EMIF_SDTIM2 Register, and TRM explains that is:

Minimum number of DDR3_CLKOUT cycles between read and write
date phases, minus 1. This is not an SDRAM timing parameter. The
value depends on the board topology supported.
For single rank: reg_t_RTW= (((2*dqs_delay_for_cs0)+tDQSCK+
wr_leveling_tolerance)/clock_period)-1
For dual rank: reg_t_RTW=
((dqs_delay_for_cs0+dqs_delay_for_cs1+
absolute(command_delay_for_cs0-
command_delay_for_cs1)+tDQSCK+
wr_leveling_tolerance)/clock_period)-1

They are not sure what values could be used for dqs_delay_for_cs0, tDQSCK, wr_leveling_tolerance and clock_period.

TI: Most customers leave this value at its maximum setting of 7. These delays are discussed in the DDR3 Design Requirements for KeyStone Devices Application Report (SPRABI1C) in sections 6.3.1.9 and 6.3.1.10 regarding KS-I devices but the terminology is similar. The following 2 sections are associated with KS-II but the equations are not shown since the limits are beyond the range of supported topologies. Depending on your layout, you should be able to use a value of 3 or 4. We recommend that you fully qualify your DDR3 implementation for robust operation using 7 in this field. Thereafter, you can test lower values. Note that setting this value too low will result in unstable operation.

4. In the Controller Register sheet, there is a bit field "T_CSTA " in EMIF_SDTIM4 Register, and TRM explains that is:

Minimum DDR3_CLKOUT cycles between write-to-write or read-to-read data phases to different chip selects, minus 1.

If DDR3L spec defined CAS#- to-CAS# command delay (tCCD)＝4CLOCK, they would apply 3 for this bit field. Correct?

TI: No, this term is applied to back to back accesses of the same type but to different chip selects. Since the SDRAM that you have chosen is a single-die device and you do not appear to be using a topology with a 2^nd chip select, this value is a “don’t care”.

5. In the Controller Register sheet, there is a bit field "ZQ_REFINTERVAL" in EMIF_ZQ_CONFIG Register, and TRM explains that is:

Number of refresh periods between ZQCS commands, minus one.
This field supports between one refresh period to 256 ms between
ZQCS calibration commands. Refresh period is defined by the
EMIF_SDRFC[15-0] REFRESH_RATE field.
ZQ_REFINTERVAL = number of refresh periods between ZQCS
commands.
The interval is calculated as = 0.5% / [(Tsens x Tdriftrate) + (Vsens x
Vdriftrate)].
Tsens = max (dRTTdT, dRONdTM) from the memory device data
sheet.
Vsens = max(dRTTdV, dRONdVM) from the memory device data
sheet
Tdriftrate = drift rate in o C/second. This is the temperature drift rate
that the SDRAM is subject to in the application. Vdriftrate = drift rate
in mV/second. This is the voltage drift rate that the SDRAM is
subject to in the application.
Example:
If Tsens= 1.5%/ o C, Vsens = 0.15%/mV, Tdriftrate = 1.2 o C/second
and Vdriftrate = 10mV/second,
Interval = 0.5/[(1.5 x 1.2) + (0.15 x 10)] = 152ms.
Since refresh interval = 7.8µs, ZQ_REFINTERVAL = 152ms/7.8µs =
4C1Fh

Here, they could not find Tdriftrate and Vdriftrate from the DDR3L datasheet. Could you please take a look at DDR3L datasheet and let us know if what parameters are used for these variables.

TI: These are not terms from the DDR3 SDRAM datasheet. These are voltage and temperature drift rates in your system. Section 3.5.3 of the Keystone II DDR3 Initialization Application Report (SPRABX7) discusses that the standard configuration for this parameter that we recommend is 100ms. This is the default in the REG_CALC worksheet. The ZQCS calibration period can be lengthened based on your system modeling.

Tom