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AM3715: GPMC example for access to external 8-bit device

Part Number: AM3715

Hi,

customer wants to connect an external 8-bit device on data bus (GPMC_D0-D7).

In TI_AM37x_TechRefManual_sprugn4q.pdf seems to be no example how to manage this by HW.

- Any examples for

a muxed address/Data bus ?

a non-muxed address/data bus (synchronous/asynchronous) ?

- On which port is A0 (8-bit access) ?

  • Hi Dirk,

    You can refer them to the AM335x TRM Rev. P, which has a more detailed description of the GPMC.
  • Hi Biser,

    customer came back and complains:

     

    After comparing TRM AM335x vs TRM AM3715 he found significant differences in GPMC:

    AM335x:

    Here adress-signals: GPMC_A[27:0] and address/datasignals GPMC_AD[15:0].

    AM3715:

    Here adress-signals: GPMC_A[11:1] and address/datasignals GPMC_D[15:0].

    Here no GPMC_A0 existing!!?

     

    To decode an external 8 bit peripheral with a 8-Bit (Byte) data bus he needs A0.

    So question again:

    Q1:

    Where is A0 on a non-multiplexed adressbus for 8-Bit Device?

    GPMC_A1 = A0; GPMC_A2 = A1 etc .

    Where is A0 at non-multiplexed adressbus for 8-Bit Device? (adressbus latched)

    GPMC_D0 = A0; GPMC_D1 = A1 etc.

     

     

    GPMC to 8Bit non multiplexed Memory

     

     

    GPMC to 8Bit multiplexed Memory

     

     

     

    Q2: Is there a picture (AM3715) exisitng for these modes?

     

    He need to realise this system:

     

     

     

     

     

  • Hi,

    any news on this topic ?
  • Hi Dirk,

    Following up with what was discussed in email...

    It appears OMAP3630/ AM3715 did not bond out the GPMC_A0 signal that is necessary to address an 8-bit memory in non-muxed mode.
    I do not know why it was not bonded out.

    Addressing an 8-bit non-muxed device will require A0. Other devices have the GPMC_A0 pin bonded out, and can therefore address 8-bit memories.

    Since the AD-mux mode passes address over the Address/Data pins (AD15-AD0), AD0 can be used for A0 when AD-mux mode is used.

    Certain glue-logic can be used to latch the Address from the ADn pins and then drive the address to the address pins of the memory device/FPGA. I imagine that glue logic would look something like a x16 flop that latches the address lines during a low pulse of ADVn. If GPMC is synchronous, then the latch edge should be the rising clock edge while ADVn is low. If asynch, I think the rising edge of ADVn should work, but the ADVn signal may also need to be delayed to satisfy the address to ADVn setup time of the memory device/FPGA.

    Regards,
    Mark