AM4376: DDR3 Timings

Hi Shinji,

You should start from the below docs:

http://www.ti.com/tool/sitara-ddr-config-tool

www.ti.com/.../sprac70.pdf

Regards,
Pavel

Dear Pavel,

Thank you for your quick reply. I already read the document with related ones. But I was not able to find the information.

I need to know the margin of the interface between AM4376 EMIF and DDR3 memories exactly.

So, I am very happy if you let me know the document to have the information or the value.

Thank you.

Regards,
Shinji

Dear Pavel,

Thank you very much for your reply. But I already read the section some times and it does not seem to be the explanation about the controller timing I want to know in the section and also other docs. Could you please check where is it in what doc and section?

I have another related questions. It is about ibis model of AM4376. Can I continue to post the questions here or should I make a new thread for that, let me know.

Thank you.

Regards,
Shinji

Shinji,

I will forward your questions to our DDR expert. He will reply here in this e2e thread. There might be some delay due to holidays.

Regards,
Pavel

Dear Pavel,
Thank you very much. I will wait for the reply.

I have another question.

I am performing SI analysis of the DDR3 Interface.
Ibis model I am using is sprm636.ibs (Rev1.0).
It has so many IO models per each pins, and I do not understand the meaning of each short letter in the model selector.
For example, when I want to choose 44 ohms driver for the DQ pin in output, which model should I choose in the following list?

*****************************************************************************************
| Usage I/O#1.2/1.35/1.5###BCSHTLTCSCTVPBFZ_SSDHV.PAD
| Base model BCSHTLTCSCTVPBFZ_SSDHV
|*****************************************************************************************
[Model Selector] Selector_12
[Model Selector] Selector_12
Model_1009 3-STATE,1.2V,SR11, 12MA,10%,SR11_12MA_10PER_1P2
Model_1010 3-STATE,1.2V,SR10, 5MA,10%,SR10_5MA_10PER_1P2
Model_1011 3-STATE,1.2V,SR10, 9MA,10%,SR10_9MA_10PER_1P2
Model_1012 3-STATE,1.2V,SR01, 5MA,10%,SR01_5MA_10PER_1P2
Model_1013 3-STATE,1.2V,SR11, 5MA,10%,SR11_5MA_10PER_1P2
Model_1014 3-STATE,1.2V,SR00, 7MA,10%,SR00_7MA_10PER_1P2
Model_1015 3-STATE,1.2V,SR01, 9MA,10%,SR01_9MA_10PER_1P2
....

I was not able to find any key word of the driver level in the list.

If there is any document to help me to understand the models, let me know.
Any help is appreciated.

Thank you.

Regards,
Shinji

Shinji,

Please see the following tables in the AM437x Technical Reference Manual:

• Table 7-8. DDR Slew Rate Control Settings
• Table 7-9. DDR Impedance Control Settings

The SR terminology relates to the slew rate (i.e. Table 7-8) while the numbers like 5MA, 7MA, etc. refer to the drive strength (Table 7-9).  The 9MA entry corresponds to 44 ohms.

Although the following wiki page was written for AM335x, you might find it helpful for getting the general idea on AM437x:

http://processors.wiki.ti.com/index.php/How_to_use_the_AM335x_IBIS_Models

FYI, that final section on verifying your configuration is also applicable to AM437x if you use its associated script:

http://git.ti.com/sitara-dss-files/am43xx-dss-files/blobs/raw/master/am43xx-ddr-analysis.dss

Best regards,
Brad

Hi Brad,

I had the same questions as Shinji. Thank you very much for providing resources. As far as his first question goes, I don't see any information with regards to the timing parameters of the controller in the references you have provided. Could you please clarify where I can find this information?

Thank you,

Sean

The skew-related parameters that were mentioned are not things you program. They are adjusted dynamically by the hardware leveling process.

Hi Brad,

The information that Shinji was requesting is needed for a Hyperlynx .v simulation file. Hyperlynx allows for write and read leveling but these parameters specified should be specific to the delays of the controller :

     All cycles:
        tACCSkew          Output delay skew from CK falling to Addr/Cmd/Ctl (+/-)

     Write cycles:
       tCKDQS            Output delay skew from CK rising to DQS rising (+/-)
       tDQSDQQ           Output delay skew from DQS to DQ (+/-)

     Read cycles
       tDS               Minimum DQ to DQS setup time, with 1/4 cycle DQS shift
       tDH               Minimum DQS to DQ hold time, with 1/4 cycle DQS shift

Here is a link speaking to each of the specific parameters for Hyperlynx testing :

The delays in the DQS line can then be modified with the leveling process. But these parameters should be specific to the controller itself. Are you aware of any place I might be able to find this? Or are you aware of any .v Hyperlynx controller files for this specific processor (AM4376)?

Thanks,

Sean

Hi Pavel,

> I will forward your questions to our DDR expert. He will reply here in this e2e thread. There might be some delay due to holidays.

I am still waiting for the information I asked in the first post. Sean is also waiting ...

Thanks again.

Regards,

Shinji