Linux的/ TDA2E： run app.out, then hang at Bsp_platformSetPllFreq

SJay

Other Parts Discussed in Thread: TDA2E, SYSCONFIG

產品編號： TDA2E

工具/軟件： Linux

Our own PCBA,

Some of them will hang on the Bsp_platformSetPllFreq function after executing app.out, but the other will run successfully.

We have two display modes, HDMI or LCD.

Both have a chance to fail.

I have tracked the code and added some logs, as shown below,

I also execute dss_clockdumps.sh to dump the information.

If I execute app.out fail,

and then I run dss_clockdumps.sh script,

it also hang, the log is as follows,

Also, after trying to annotate Bsp_platformSetPllFreq,

It becomes hang at Bsp_platformSetVencClkSrc.

If both are annotated,

It can execute app.out success, but the vedio will continue to move left and right

This is the dss part of my dts, as shown below,

below is my display config,

static Void ChainsCommon_SetDctrlConfig(
                                DisplayCtrlLink_ConfigParams *pPrm,
                                DisplayCtrlLink_OvlyParams *ovlyPrms,
                                DisplayCtrlLink_OvlyPipeParams *pipeOvlyPrms,
                                UInt32 displayType,
                                UInt32 displayWidth,
                                UInt32 displayHeight)
{
    DisplayCtrlLink_VencInfo *pVInfo;

    pPrm->numVencs = 1;
    pPrm->tiedVencs = 0;

    pVInfo = &pPrm->vencInfo[0];

    pVInfo->tdmMode = DISPLAYCTRL_LINK_TDM_DISABLE;
    if(displayType == CHAINS_DISPLAY_TYPE_LCD_7_INCH)
    {
        pPrm->deviceId = DISPLAYCTRL_LINK_USE_LCD;
        pVInfo->vencId = SYSTEM_DCTRL_DSS_VENC_LCD1;
        pVInfo->outputPort = SYSTEM_DCTRL_DSS_DPI1_OUTPUT;
        pVInfo->vencOutputInfo.vsPolarity    =   SYSTEM_DCTRL_POLARITY_ACT_LOW;
        pVInfo->vencOutputInfo.hsPolarity    =   SYSTEM_DCTRL_POLARITY_ACT_LOW;

        /* Below are of dont care for EVM LCD */
        pVInfo->vencOutputInfo.fidPolarity      =   SYSTEM_DCTRL_POLARITY_ACT_LOW;
        pVInfo->vencOutputInfo.actVidPolarity   =   SYSTEM_DCTRL_POLARITY_ACT_LOW;

        pVInfo->mInfo.standard                  =   SYSTEM_STD_CUSTOM;
        pVInfo->mInfo.width                     =   displayWidth;
        pVInfo->mInfo.height                    =   displayHeight;
        pVInfo->mInfo.scanFormat                =   SYSTEM_SF_PROGRESSIVE;
        pVInfo->mInfo.pixelClock                =   29232u;
        pVInfo->mInfo.fps                       =   60U;
        pVInfo->mInfo.hFrontPorch               =   40u;
        pVInfo->mInfo.hBackPorch                =   40u;
        pVInfo->mInfo.hSyncLen                  =   48u;
        pVInfo->mInfo.vFrontPorch               =   13u;
        pVInfo->mInfo.vBackPorch                =   29u;
        pVInfo->mInfo.vSyncLen                  =   3u;
        pVInfo->vencDivisorInfo.divisorLCD      =   1;
        pVInfo->vencDivisorInfo.divisorPCD      =   4;

        pVInfo->vencOutputInfo.dataFormat       =   SYSTEM_DF_RGB24_888;
        pVInfo->vencOutputInfo.dvoFormat        =
                                    SYSTEM_DCTRL_DVOFMT_GENERIC_DISCSYNC;
        pVInfo->vencOutputInfo.videoIfWidth     =   SYSTEM_VIFW_24BIT;

        pVInfo->vencOutputInfo.pixelClkPolarity =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;
        pVInfo->vencOutputInfo.aFmt             =   SYSTEM_DCTRL_A_OUTPUT_MAX;

        /* Configure overlay params */

        ovlyPrms->vencId                       = SYSTEM_DCTRL_DSS_VENC_LCD1;
    }
    else if(displayType == CHAINS_DISPLAY_TYPE_LCD_10_INCH)
    {
        pPrm->deviceId = DISPLAYCTRL_LINK_USE_LCD;
        pVInfo->vencId = SYSTEM_DCTRL_DSS_VENC_LCD1;
        pVInfo->outputPort = SYSTEM_DCTRL_DSS_DPI1_OUTPUT;
        pVInfo->vencOutputInfo.vsPolarity    =   SYSTEM_DCTRL_POLARITY_ACT_LOW;
        pVInfo->vencOutputInfo.hsPolarity    =   SYSTEM_DCTRL_POLARITY_ACT_LOW;

        /* Below are of dont care for EVM LCD */
        pVInfo->vencOutputInfo.fidPolarity      =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;
        pVInfo->vencOutputInfo.actVidPolarity   =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;

        pVInfo->mInfo.standard                  =   SYSTEM_STD_CUSTOM;
        pVInfo->mInfo.width                     =   displayWidth;
        pVInfo->mInfo.height                    =   displayHeight;
        pVInfo->mInfo.scanFormat                =   SYSTEM_SF_PROGRESSIVE;
/*        pVInfo->mInfo.pixelClock                =   74500U;
        pVInfo->mInfo.fps                       =   60U;
        pVInfo->mInfo.hBackPorch                =   80U;
        pVInfo->mInfo.hSyncLen                  =   62U;
        pVInfo->mInfo.hFrontPorch               =   48U;
        pVInfo->mInfo.vBackPorch                =   12U;
        pVInfo->mInfo.vSyncLen                  =   35U;
        pVInfo->mInfo.vFrontPorch               =   6U;*/
 	pVInfo->mInfo.pixelClock    = 74250U;
  	pVInfo->mInfo.fps      = 60U; 
  	pVInfo->mInfo.hBackPorch    = 220U;
  	pVInfo->mInfo.hSyncLen     = 40U;
  	pVInfo->mInfo.hFrontPorch    = 110U;
  	pVInfo->mInfo.vBackPorch    = 20U;
  	pVInfo->mInfo.vSyncLen     = 5U;
  	pVInfo->mInfo.vFrontPorch    = 5U;
        pVInfo->vencDivisorInfo.divisorLCD      =   1;
        pVInfo->vencDivisorInfo.divisorPCD      =   1;

        pVInfo->vencOutputInfo.dataFormat       =   SYSTEM_DF_RGB24_888;
        pVInfo->vencOutputInfo.dvoFormat        =
                                    SYSTEM_DCTRL_DVOFMT_GENERIC_DISCSYNC;
        pVInfo->vencOutputInfo.videoIfWidth     =   SYSTEM_VIFW_24BIT;

        pVInfo->vencOutputInfo.pixelClkPolarity =   SYSTEM_DCTRL_POLARITY_ACT_LOW;
        pVInfo->vencOutputInfo.aFmt             =   SYSTEM_DCTRL_A_OUTPUT_MAX;

        /* Configure overlay params */

        ovlyPrms->vencId                       = SYSTEM_DCTRL_DSS_VENC_LCD1;
    }
    else if (displayType ==
        CHAINS_DISPLAY_TYPE_LDC_10_INCH_LCDCTRL_TC358778_MIPI_DSI_1920_1200)
    {
        pPrm->deviceId = DISPLAYCTRL_LINK_USE_LCD;
        pVInfo->vencId = SYSTEM_DCTRL_DSS_VENC_LCD1;
        pVInfo->outputPort = SYSTEM_DCTRL_DSS_DPI1_OUTPUT;
        pVInfo->vencOutputInfo.vsPolarity    =   SYSTEM_DCTRL_POLARITY_ACT_LOW;
        pVInfo->vencOutputInfo.hsPolarity    =   SYSTEM_DCTRL_POLARITY_ACT_LOW;

        /* Below are of dont care for EVM LCD */
        pVInfo->vencOutputInfo.fidPolarity      =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;
        pVInfo->vencOutputInfo.actVidPolarity   =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;

        pVInfo->mInfo.standard                  =   SYSTEM_STD_CUSTOM;
        pVInfo->mInfo.width                     =   displayWidth;
        pVInfo->mInfo.height                    =   displayHeight;
        pVInfo->mInfo.scanFormat                =   SYSTEM_SF_PROGRESSIVE;
        pVInfo->mInfo.pixelClock                =   147000U;
        pVInfo->mInfo.fps                       =   60U;
        pVInfo->mInfo.hBackPorch                =   32U;
        pVInfo->mInfo.hSyncLen                  =   16U;
        pVInfo->mInfo.hFrontPorch               =   32U;
        pVInfo->mInfo.vBackPorch                =   16U;
        pVInfo->mInfo.vSyncLen                  =   2U;
        pVInfo->mInfo.vFrontPorch               =   7U;
        pVInfo->vencDivisorInfo.divisorLCD      =   1;
        pVInfo->vencDivisorInfo.divisorPCD      =   1;

        pVInfo->vencOutputInfo.dataFormat       =   SYSTEM_DF_RGB24_888;
        pVInfo->vencOutputInfo.dvoFormat        =
                                    SYSTEM_DCTRL_DVOFMT_GENERIC_DISCSYNC;
        pVInfo->vencOutputInfo.videoIfWidth     =   SYSTEM_VIFW_24BIT;

        pVInfo->vencOutputInfo.pixelClkPolarity =   SYSTEM_DCTRL_POLARITY_ACT_LOW;
        pVInfo->vencOutputInfo.aFmt             =   SYSTEM_DCTRL_A_OUTPUT_MAX;

        /* Configure overlay params */

        ovlyPrms->vencId                       = SYSTEM_DCTRL_DSS_VENC_LCD1;
    }
    else if(displayType == CHAINS_DISPLAY_TYPE_HDMI_720P
            || displayType == CHAINS_DISPLAY_TYPE_HDMI_1080P)
    {
        pPrm->deviceId = DISPLAYCTRL_LINK_USE_HDMI;
        pVInfo->vencId = SYSTEM_DCTRL_DSS_VENC_HDMI;
        pVInfo->outputPort = SYSTEM_DCTRL_DSS_HDMI_OUTPUT;
        pVInfo->vencOutputInfo.vsPolarity       =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;
        pVInfo->vencOutputInfo.hsPolarity       =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;

        /* Below are of dont care for EVM LCD */
        pVInfo->vencOutputInfo.fidPolarity      =   SYSTEM_DCTRL_POLARITY_ACT_LOW;
        pVInfo->vencOutputInfo.actVidPolarity   =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;

        pVInfo->vencOutputInfo.dataFormat       =   SYSTEM_DF_RGB24_888;
        pVInfo->vencOutputInfo.dvoFormat        =
                                    SYSTEM_DCTRL_DVOFMT_GENERIC_DISCSYNC;
        pVInfo->vencOutputInfo.videoIfWidth     =   SYSTEM_VIFW_24BIT;

        pVInfo->vencOutputInfo.pixelClkPolarity =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;
        pVInfo->vencOutputInfo.aFmt             =   SYSTEM_DCTRL_A_OUTPUT_MAX;

        /* Configure overlay params */

        ovlyPrms->vencId                        = pVInfo->vencId;
    }
    else if(displayType == CHAINS_DISPLAY_TYPE_FPD)
    {
        pPrm->deviceId = DISPLAYCTRL_LINK_USE_LCD;
        pVInfo->vencId = SYSTEM_DCTRL_DSS_VENC_LCD3;
        pVInfo->outputPort = SYSTEM_DCTRL_DSS_DPI3_OUTPUT;
        pVInfo->mInfo.width                     =   displayWidth;
        pVInfo->mInfo.height                    =   displayHeight;
        pVInfo->mInfo.pixelClock                =   74250;
        pVInfo->mInfo.fps                       =   60U;
        pVInfo->mInfo.hBackPorch                =   148U;
        pVInfo->mInfo.hSyncLen                  =   44U;
        pVInfo->mInfo.hFrontPorch               =   88U;
        pVInfo->mInfo.vBackPorch                =   15U;
        pVInfo->mInfo.vSyncLen                  =   5U;
        pVInfo->mInfo.vFrontPorch               =   2U;
        pVInfo->vencDivisorInfo.divisorLCD      =   1;
        pVInfo->vencDivisorInfo.divisorPCD      =   1;
        pVInfo->vencOutputInfo.vsPolarity       =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;
        pVInfo->vencOutputInfo.hsPolarity       =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;

        /* Below are of dont care for EVM LCD */
        pVInfo->vencOutputInfo.fidPolarity      =   SYSTEM_DCTRL_POLARITY_ACT_LOW;
        pVInfo->vencOutputInfo.actVidPolarity   =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;

        pVInfo->vencOutputInfo.dataFormat       =   SYSTEM_DF_RGB24_888;
        pVInfo->vencOutputInfo.dvoFormat        =
                                    SYSTEM_DCTRL_DVOFMT_GENERIC_DISCSYNC;
        pVInfo->vencOutputInfo.videoIfWidth     =   SYSTEM_VIFW_24BIT;

        pVInfo->vencOutputInfo.pixelClkPolarity =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;
        pVInfo->vencOutputInfo.aFmt             =   SYSTEM_DCTRL_A_OUTPUT_MAX;

        /* Configure overlay params */

        ovlyPrms->vencId                        = pVInfo->vencId;
    }
    else
    {
        OSA_assert(0);
    }

    if(displayType == CHAINS_DISPLAY_TYPE_HDMI_720P)
    {
        pVInfo->mInfo.standard                  =   SYSTEM_STD_720P_60;

    }
    else if (displayType == CHAINS_DISPLAY_TYPE_HDMI_1080P)
    {
        pVInfo->mInfo.standard                  =   SYSTEM_STD_1080P_60;
    }
    else if (displayType == CHAINS_DISPLAY_TYPE_FPD)
    {
        pVInfo->mInfo.standard                  =   SYSTEM_STD_720P_60;
    }

    /* TODO Dont know what to set here */
    pVInfo->mode = 0;
    pVInfo->isInputPipeConnected[0] =
                    TRUE;
    pVInfo->isInputPipeConnected[1] =
                    TRUE;
    pVInfo->isInputPipeConnected[2] =
                    TRUE;
    pVInfo->isInputPipeConnected[3] =
                    TRUE;
    pVInfo->writeBackEnabledFlag = FALSE;


    /* Setting other overlay parameters common to both Venc */

    ovlyPrms->deltaLinesPerPanel   = 0;
    ovlyPrms->alphaBlenderEnable   = 0;
    ovlyPrms->backGroundColor      = 0x10;
    ovlyPrms->colorKeyEnable       = 1;
    ovlyPrms->colorKeySel          = SYSTEM_DSS_DISPC_TRANS_COLOR_KEY_SRC;
    ovlyPrms->ovlyOptimization     = SYSTEM_DSS_DISPC_OVLY_FETCH_ALLDATA;
    ovlyPrms->transColorKey        = DRAW2D_TRANSPARENT_COLOR;

    /* Setting overlay pipe parameters */

    pipeOvlyPrms[0].pipeLine = SYSTEM_DSS_DISPC_PIPE_VID1;
    pipeOvlyPrms[0].globalAlpha = 0xFF;
    pipeOvlyPrms[0].preMultiplyAlpha = 0;
    pipeOvlyPrms[0].zorderEnable = TRUE;
    pipeOvlyPrms[0].zorder = SYSTEM_DSS_DISPC_ZORDER0;

    pipeOvlyPrms[1].pipeLine = SYSTEM_DSS_DISPC_PIPE_VID2;
    pipeOvlyPrms[1].globalAlpha = 0xFF;
    pipeOvlyPrms[1].preMultiplyAlpha = 0;
    pipeOvlyPrms[1].zorderEnable = TRUE;
    pipeOvlyPrms[1].zorder = SYSTEM_DSS_DISPC_ZORDER1;

    pipeOvlyPrms[2].pipeLine = SYSTEM_DSS_DISPC_PIPE_VID3;
    pipeOvlyPrms[2].globalAlpha = 0xFF;
    pipeOvlyPrms[2].preMultiplyAlpha = 0;
    pipeOvlyPrms[2].zorderEnable = TRUE;
    pipeOvlyPrms[2].zorder = SYSTEM_DSS_DISPC_ZORDER2;

    pipeOvlyPrms[3].pipeLine = SYSTEM_DSS_DISPC_PIPE_GFX1;
    pipeOvlyPrms[3].globalAlpha = 0xFF;
    pipeOvlyPrms[3].preMultiplyAlpha = 0;
    pipeOvlyPrms[3].zorderEnable = TRUE;
    pipeOvlyPrms[3].zorder = SYSTEM_DSS_DISPC_ZORDER3;

}

Can someone see if there are any problems?

My environment is tda2eg and visionsdk_3.02

over 5 years ago

0 Yordan Kamenov over 5 years ago

TI__Mastermind 42515 points

Hi,

please translate your post to English. E2E forum is supported only in English.

Regards,
Yordan

0 SJay over 5 years ago in reply to Yordan Kamenov

Expert 1615 points

sorry , I accidentally pressed to the google translation option.

0 Prasad Konnur over 5 years ago in reply to SJay

TI__Expert 6065 points

Hi,

Can you try to check where the code is hangs in pll frequency setting?
If you have a debugger you can connect to the m4 core and try to check.

If you comment out the pll configuration the pixel clk sent outwill not be proper and display will be correct.

Regards,
Prasad

0 SJay over 5 years ago in reply to Prasad Konnur

Expert 1615 points

Hi,

i use dss_clockdumps.sh,

and this is the logs when running LCD success.

=====================DSS clock script===================
Dumps internal clocks and muxes of DSS

CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x000002A6
video1 PLL : Enabled
video2 PLL : Disabled
HDMI PLL : Disabled
DSI1_A_CLK mux : DPLL Video1
DSI1_B_CLK mux : DPLL video2
DSI1_C_CLK mux : DPLL Video1

DSS_CTRL (0x58000040) = 0x00010001
2: LCD1 clk switch : DSI1_A_CLK
3: LCD2 clk switch : DSS clk
10: LCD3 clk switch : DSS clk
1: func clk switch : DSS clk
13: DPI1 output : LCD1

DSS_STATUS (0x5800005C) = 0x01408A82

DSI_CLK_CTRL (0x58004054) = 0x80004001

CM_DSS_CLKSTCTRL (0x4A009100) = 0x00061F03

CM_DSS_DSS_CLKCTRL (0x4A009120) = 0x00003F02

========================================================
Register dump for DPLL video1
|----------------------------|
| Address (hex) | Data (hex) |
|----------------------------|
| 0x58004300 | 0x00000018 |
| 0x58004304 | 0x00002A83 |
| 0x58004308 | 0x00000000 |
| 0x5800430C | 0x008948FE |
| 0x58004310 | 0x02616108 |
| 0x58004314 | 0x00000004 |
| 0x58004318 | 0x00000000 |
| 0x5800431C | 0x00000000 |
| 0x58004320 | 0x00000000 |
|----------------------------|
Details for DPLL video1
PLL status : Locked
M4 hsdiv(1) : Active
M5 hsdiv(2) : inactive
M6 hsdiv(3) : inactive
M7 hsdiv(4) : Active

PLL_REGM = 1188
PLL_REGN = 127
M4 DIV = 4
M6 DIV = 4
M7 DIV = 0

Clock calculations (DPLL video1)
sysclk = 20000000
DCO clk = sysclk * 2 * REGM / (REGN + 1) = 371250000
M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 74250000
M6clk (clkcout3) = DCO clk / (M6 DIV + 1) = 0
M7clk (clkcout4) = DCO clk / (M7 DIV + 1) = 371250000

========================================================
Clock O/P of MUXes
./debug_dss_clockdumps_old.sh: line 229: * 1000000 : syntax error: operand expected (error token is "* 1000000 ")

and this is the logs when running LCD fail.

=====================DSS clock script===================
Dumps internal clocks and muxes of DSS

CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x000002AE
video1 PLL : Enabled
video2 PLL : Disabled
HDMI PLL : Disabled
DSI1_A_CLK mux : DPLL HDMI
DSI1_B_CLK mux : DPLL video2
DSI1_C_CLK mux : DPLL Video1

DSS_CTRL (0x58000040) = 0x00010000
2: LCD1 clk switch : DSS clk
3: LCD2 clk switch : DSS clk
10: LCD3 clk switch : DSS clk
1: func clk switch : DSS clk
13: DPI1 output : LCD1

DSS_STATUS (0x5800005C) = 0x01408A81

DSI_CLK_CTRL (0x58004054) = 0x80004001

CM_DSS_CLKSTCTRL (0x4A009100) = 0x00061F03

CM_DSS_DSS_CLKCTRL (0x4A009120) = 0x00043F02

========================================================
Register dump for DPLL video1
|----------------------------|
| Address (hex) | Data (hex) |
|----------------------------|
| 0x58004300 | 0x00000018 |
| 0x58004304 | 0x00018049 |
| 0x58004308 | 0x00000000 |
| 0x5800430C | 0x008948FE |
| 0x58004310 | 0x0261A008 |
| 0x58004314 | 0x00000004 |
| 0x58004318 | 0x00000000 |
| 0x5800431C | 0x00000000 |
| 0x58004320 | 0x00000000 |
|----------------------------|
Details for DPLL video1
PLL status : inactive
M4 hsdiv(1) : inactive
M5 hsdiv(2) : inactive
M6 hsdiv(3) : inactive
M7 hsdiv(4) : inactive

PLL_REGM = 1188
PLL_REGN = 127
M4 DIV = 4
M6 DIV = 4
M7 DIV = 0

Clock calculations (DPLL video1)
sysclk = 20000000
DCO clk = sysclk * 2 * REGM / (REGN + 1) = 0
M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 0
M6clk (clkcout3) = DCO clk / (M6 DIV + 1) = 0
M7clk (clkcout4) = DCO clk / (M7 DIV + 1) = 0

========================================================
Clock O/P of MUXes
./debug_dss_clockdumps_old.sh: line 229: * 1000000 : syntax error: operand expected (error token is "* 1000000 ")

When it fails,the item "DPLL Video1" will be set to "DPLL HDMI", not "DPLL Video1".

and PLL status will be inactive

Do you know why?

inactive

0 SJay over 5 years ago in reply to Prasad Konnur

Expert 1615 points

Hi,
the function PMLIBVideopllSetFreq will return fail,

and if LCD case fail, why the DSI1_A_CLK mux will become to DPLL HDMI not DPLL Video1

Suddenly thought that we have to take off the oscillator1, will it affect?

0 Prasad Konnur over 5 years ago in reply to SJay

TI__Expert 6065 points

Hi,

Can you check what are the parameters passed to the PMLIBVideopllSetFreq during the successful and failure cases?
LCD clock can be sourced from DPLL Video1 or DPLL Hdmi, you can refer the clock diagram in the TRM.

I did not get what you mean by "we have to take off the oscillator1" can you tell what you are trying to do?

Regards,
Prasad

0 SJay over 5 years ago in reply to Prasad Konnur

Expert 1615 points

Hi,

Our previous version of PCBA did not have this display problem,

and one of the differences in this version is that we feel that OSC1 is not used,

so I took it off, and I observed that OSC1 seems to be related to DPLL_ABE,

I want to ask if this is caused by this factor.

The parameters passed to the PMLIBVideopllSetFreq during the successful and failure cases are the same,as follows,

videopllId=175, pixelClk=74250, maxorMinMN=1, timeDelay=-1

0 SJay over 5 years ago in reply to Prasad Konnur

Expert 1615 points

Hi,

Summarize the current situation,

Whether it is hdmi output or LCD output,

It seems that I will encounter the problem of PLL lock failure.

The previous version customized PCBAs does not,

One of the differences between the current version and the previous version is that OSC1 is removed.

In dra7xx-clocks.dtsi, do you know whick parts of sys_clkin2 must to be modify and how to modify?

In addition, it was found that the Ball pin AC15(xi_osc1) did not follow the recommended on the spec to connect GND after removing OSC1,

is this part will cause pll to lock?

SJay

0 SJay over 5 years ago in reply to Prasad Konnur

Expert 1615 points

Hi,
i trace hdmi case,
in packages\ti\drv\vps\src\vpslib\hal\src\vpshal_dssHdmi.c
function halHdmiPllInit at line 542
when fail, there was timeout for waiting the lock bit is set in PLL status.

the pllInfo info when fail or success are the same,as follows

pllInfo info : regn=16,regm=594,regmf=0,regm2=1,regsd=9,dcofreq=0

Jay

0 Prasad Konnur over 5 years ago in reply to SJay

TI__Expert 6065 points

Hi,

Can you check what you see in the below register?
CM_CLKSEL_HDMI_PLL_SYS (0x4AE06164).
From the clock tree you can see that this selects the HDMI pll input clock from sysclock1 or sysclock2.
From your previous replies you have removed sysclock2 if I am not wrong.
Can you check this?

Regards,
Prasad

0 SJay over 5 years ago in reply to Prasad Konnur

Expert 1615 points

Hi,
it is from sysclock1,when failed to lock pll

[HOST] [IPU2 ] 27.365887 s: smallyouyou =========+++++++ halHdmiPllInit fail!!!
[HOST] [IPU2 ] 27.365979 s: dispcore/src/vpscore_dctrl.c @ Line 1587:
[HOST] [IPU2 ] 27.366070 s: Failed to lock PLL
[HOST] [IPU2 ] 27.367443 s: dispdrv/src/vpsdrv_dctrl.c @ Line 698:
[HOST] [IPU2 ] 27.367534 s: Core control: Set Config failed!!
[HOST] [IPU2 ] 27.367595 s: Assertion @ Line: 894 in displayCtrlLink_drv.c: retVal == SYSTEM_LINK_STATUS_SOK : failed !!!
^Croot@dra7xx-evm:~# devmem2 0x4AE06164
/dev/mem opened.
Memory mapped at address 0xb6f6c000.
Read at address 0x4AE06164 (0xb6f6c164): 0x00000000
root@dra7xx-evm:~#

0 SJay over 5 years ago in reply to Prasad Konnur

Expert 1615 points

Hi Prasad,

Is there any other possibility?

Regardless of the LCD or HDMI display, the PLL_STATUS[0] and [6] values always show 1,

Represents "Reference input inactive" & "PLL bypass",

I have found a similar situation in the i932 issue in sprz428d.pdf,

trying the workaround, run the PLL_GO process again after the failure, but still fail

S Jay

0 Prasad Konnur over 5 years ago in reply to SJay

TI__Expert 6065 points

Hi,

You had mentioned earlier that the OSC1 is removed in your board,

Is this Sysclk1 or sysclk2 that is removed?

Are there any other changes in the board?

Regards,

Prasad

0 SJay over 5 years ago in reply to Prasad Konnur

Expert 1615 points

Hi,

I have cross-tested this part with the previous and now pcba versions.

i removed the components from the previous version,

just like i had removed from now pcba version.

But after running the same version of code on the previous version,

there was no same problem, pll not lock

so i think not osc lead to this situation.

also, switch osc with previous and now pcba version,

but it is the same. : (

Currently trying to take the SOC to replant,

See if it is a problem with pcba soldering.

S Jay

0 Prasad Konnur over 5 years ago in reply to SJay

TI__Expert 6065 points

Hi,

Any updates on this?

If there is no further update I'll mark this thread as closed.

Regards,
Prasad

0 SJay over 5 years ago in reply to Prasad Konnur

Expert 1615 points

Hi,

The SOC has been replanted,

But the result is still the same.

S Jay

0 SJay over 5 years ago in reply to Prasad Konnur

Expert 1615 points

Hi,

Recently made another attempt,

PLL_STATUS dumped from dss_clockdumps.sh can be observed,

when DSS fails, the value of bit3(PLL_LOSSREF) is 1,

it means we lost the reference clock,

then became bypass mode.

A video pll diagram can be found that a gating is controlled by REFEN,

and REFEN is controlled by the OCP2SCP_SYSCONFIG register,

we changed bit 0 (AUTOIDLE) to 0x0 for free-running,

so that it should never be in the state of gating,

but the result is still not improved,

there will still be a loss of the reference clock state,

Why not gating, still have a chance to cause such a result?

0 Piyali Goswami over 5 years ago in reply to SJay

TI__Mastermind 30235 points

SJay,

Can you please share the values you are reading for the below registers?

PLL_CONTROL
PLL_STATUS
PLL_GO
PLL_CONFIGURATION1
PLL_CONFIGURATION2
PLL_CONFIGURATION3
PLL_SSC_CONFIGURATION1
PLL_SSC_CONFIGURATION2
PLL_CONFIGURATION4

Thanks and Regards,

Piyali

0 SJay over 5 years ago in reply to Piyali Goswami

Expert 1615 points

Hi Piyali,

PLL_CONTROL 0x00000018
PLL_STATUS 0x00018049
PLL_GO 0x00000000
PLL_CONFIGURATION1 0x008948FE
PLL_CONFIGURATION2 0x0261A008
PLL_CONFIGURATION3 0x00000004
PLL_SSC_CONFIGURATION1 0x00000000
PLL_SSC_CONFIGURATION2 0x00000000
PLL_CONFIGURATION4 0x00000000

SJay

0 Piyali Goswami over 5 years ago in reply to SJay

TI__Mastermind 30235 points

SJay,

Apologies for the delay.

The register dump you have shared has an interesting value of the PLL_LDOPWDN and the PLL_TICOPWDN is high indicating some parts of the PLL are powered down.

Which version of the SDK are you using?

It would be good to understand whether this is the case of the DPLL portions powered off even before configuring the PLLs. Once you let us know the version, I will share the points to put a breakpoint in CCS and then see the status of these registers.

Thanks and Regards,
Piyali

0 SJay over 5 years ago in reply to Piyali Goswami

Expert 1615 points

Hi Piyali,

We use vision_sdk 3.02.

Run on linux.

SJay

0 Piyali Goswami over 5 years ago in reply to SJay

TI__Mastermind 30235 points

Thanks SJay,

You would first need to start with connecting to M4 and place a breakpoint at PMHALVideopllConfigure
ti_components/drivers/pdk_01_08_01_06/packages/ti/drv/pm/src/pmhal/prcm/V0/pmhal_videopll.c

Once you hit here after running your application, You would then need to run till PmhalVideopllGetMultiplierValueInternal and dump the values of the registers :

PLL_CONTROL
PLL_STATUS
PLL_GO
PLL_CONFIGURATION1
PLL_CONFIGURATION2
PLL_CONFIGURATION3
PLL_SSC_CONFIGURATION1
PLL_SSC_CONFIGURATION2
PLL_CONFIGURATION4

Then run to PMHALVideopllSetpllGo function and again dump the same registers.

Then run the code. If the lock is not set then the API would fail. Once you step out of PMHALVideopllConfigure, again dump the above registers.

Thanks and Regards,
Piyali

0 Piyali Goswami over 5 years ago in reply to Piyali Goswami

TI__Mastermind 30235 points

SJay,

we have not heard back from you on this one. I’m assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out) .

Thanks and Regards,
Piyali

0 SJay over 5 years ago in reply to Piyali Goswami

Expert 1615 points

Hi Piyali,

I have some work on hand so that I can't handle this problem right away.

After I have finished working on hand,

I will try your recommended test method.

Your answer is helpful to me. Thank you again.

Also ask, I seem to have seen if system is running on linux not rtos, it can not use CCS to set a breakpoint under the debug,

so if my usecase , A15 is running on linux, can i use ccs to connect m4 and set a breakpoint under the debug?

SJay

Processors

Processors forum

Linux的/ TDA2E： run app.out, then hang at Bsp_platformSetPllFreq