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OMAP-L138: RL calculation in mDDR_DDR2_Memory_Controller_Register_Calc_Rev5.xls appears to be incorrect

Part Number: OMAP-L138

The RL calculation in mDDR_DDR2_Memory_Controller_Register_Calc_Rev5.xls is RL = CL + 1 and this appears to be incorrect. The TRM and the answer below, which clarifies the TRM, both state RL = CL + BD - 1 = CL when BD = 1. Would an incorrect value of RL cause timing issues?

http://e2e.ti.com/support/processors/f/791/t/469128?tisearch=e2e-sitesearch&keymatch=%20user%3A42935

Thanks

  • You've downloaded the spreadsheet from this wiki:
    processors.wiki.ti.com/.../C674x
    right?

    Best Regards,
    Yordan
  • Hi,

    I think an inappropriate RL value could certainly cause issues with Reads.

    The read latency (RL) field that helps the DDR2/mDDR memory controller determine when to sample read data.
    The RL field should be programmed to a value equal to the CAS latency plus the round trip board delay minus 1.

    Perhaps the calculator tool is assuming a round trip delay of 2 MCLK/DDR_CLK cycle?
    RL = CL + BD - 1 = CL when BD = 2
    RL = CL + 1

    Consider also...
    The maximum value of read latency that is supported is CAS latency plus 2. (BD = 3?)
    The minimum read latency value that is supported is CAS latency plus 1 (BD = 2?)

    The below E2E post confirms that the Read Latency (RL) needs to be greater than CL by at least 1.

    That fits with the Datasheet Description of the RL field:
    "Read latency. Read latency is equal to CAS latency plus round trip board delay for data
    minus 1. The maximum value of read latency that is supported is CAS latency plus 2. The
    minimum read latency value that is supported is CAS latency plus 1. The read latency value
    is defined in number of MCLK/DDR_CLK cycles."

    e2e.ti.com/.../116609
    - Customer could not read back from the same location until I repeat the read command multiple times.
    - The Read Latency (RL) needs to be greater than CL by ateast 1.
    - The datasheet suggests a min RL = CL+1 and a max RL =7.
    - Configuring RL to 7 has resolved this issue

    I'll file a bug against the calculator tool to get some clarification about the RL calculation with BD as an input.

    Reagrds,
    Mark
  • Mark,

    Thanks for your reply.

    The customer in that E2E post originally had CL= 5 and RL = 4 (too low). Since BD=1 for any 150MHz OMAP-L138 design, RL = CL+BD-1 = CL. So RL should have been 5 for his design.

    Note that the confusion arises from the "-1" as discussed in the E2E post I referenced in my OP.

    From the TRM:

    "The RL field should be programmed to a value equal to the CAS latency plus the round trip board delay minus 1. The minimum RL value is CAS latency plus 1 and the maximum RL value is CAS latency plus 2 (again, the RL field would be programmed to these values minus 1)."

    So the min RL field value is CL+1-1 = CL, when BD=1, and the max is CL+2-1 = CL+1, when BD=2, which should never be the case for a 150MHz OMAP-L138 design.

    Regards,

    Dave Brent

  • Hi Dave,

    I filed a bug against the tool to fix the formula for RL to include the "minus 1".

    Thank you for bringing this issue to our attention.

    Regards,
    Mark
  • Mark,

    Thanks and you're welcome.

    Dave Brent