The RL calculation in mDDR_DDR2_Memory_Controller_Register_Calc_Rev5.xls is RL = CL + 1 and this appears to be incorrect. The TRM and the answer below, which clarifies the TRM, both state RL = CL + BD - 1 = CL when BD = 1. Would an incorrect value of RL cause timing issues?
http://e2e.ti.com/support/processors/f/791/t/469128?tisearch=e2e-sitesearch&keymatch=%20user%3A42935
Thanks