66AK2G12: UART PLL

Hi Kamil,
The UART module requires a clock input of 192MHz to generate the baud rates. There is a divide by two on the clock input to the UART module so the output of the UART PLL should be 384MHz. This is not possible with a 25MHz clock so we program the UART PLL to get as close as possible. In this case, we program the PLL to provid 383MHz using PLLD = 4, PLLM = 766 and OD = 9. This is not very well documented in the technical reference manual. If you are looking for a good example for the PLL programming using a 25MHz clock input, I suggest you look at the GEL file provided with CCS for the ICEK2G. That evaluation board uses a 25MHz clock as a source for the K2G.
Regards, Bill

Hi Bill,

Thanks for answer.
Actually I want to know if I can use higher frequencies than 384MHz for UART PLL. It is used as reference clock for QSPI interface and I want to go there as high as possible with frequency.

Thanks for advice
Regards
Kamil

Hi Kamil,

The PLL can generate a clock output greater than 384MHz but there is not purpose. The max QSPI_CLK frequency is 96MHz. QSPI_REF_CLK has to be 2 times greater than QSPI_DATA_BUS_CLK and 4 times greater than QSPI_CLK.  Based on this the fastest QSPI_REF_CLK which is driven by the output of the PLL is 4x96MHz or the 384MHz needed for the UART module. What is the purpose of using a faster clock?

Regards, Bill

Hi Bill,

Actually my impression is that QSPI_REF_CLK has to be at least 4 times greater than QSPI_CLK. Why would be in Figure 11-1309. Read Data Capture Logic adjustable divider for QSPI_CLK? There is QSPI_CONFIG _REG in which you can set baud rate using divisor form 2 to 32(QSPI_REF_CLK/BD). Why would be there possibilities to set it as you like if there should be one exact relation between these frequencies? Doesn't make sense to me.

Thanks for answer

Best regards

Kamil

Hi Kamil,

Your impression is correct, the QSPI_REF_CLK must be at least 4 times greater than QSPI_CLK.  The expected frequency of 384MHz from the UART PLL will give you the maximum clock rate of 96MHz using the value of 0001 for the MSTR_BAUD_DIV_FLD but you can select a number of lower frequencies. Using the value of 1111 will give you a qspi clock of 12MHz.  This gives you a broad range of frequencies for your QSPI interface. If you need to operate the interface at a lower speed than 12MHz it will limit the functionality of other IPs that use that clock.

Regards, Bill

Hi Bill,

so this means that I can use max QSPI_REF_CLK = 1536MHz (96MHz x 16). Then I can use maximum data shift range  (data shift done by QSPI_RD_DATA_CAPTURE[4-1] DELAY_FLD field), this can help synchronization with delayed data. Is that right?

Thanks

Regards

Kamil