• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 101 subscribers
  • Views 274 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TIDEP0025: About constraint on processing time of focloop

U-SK
Genius 5840 points
Part Number: TIDEP0025

Hello,

I'm looking Figure 9 in tidu701 document.

It seems that focloop must complete in a half of PWM period time.

For example, if PWM frequency is 47kHz, focloop must complete in 10.5us.

Is my understanding right?

If yes, could you tell me why the demo has to make a half of PWM cycles head room?

Is the period described "Available for other tasks" filled all by EtherCAT communication processing?

Regards,

U-SK

  • 0
    TI__Genius 10415 points
    Hi,

    Typically you want to capture the feedback data (phase currents and angle/position feedback) at a precise moment at the peak (or the middle) of your PWM cycle. This is shown by the vertical dotted line in the diagram that you are referring to.

    This feedback data is used in the FOC closed-loop algorithm to determine the PWM values that will be used in the next PWM cycle. For this reason, you need to complete the FOC algorithm and put the PWM values into the PWM shadow registers before the next PWM cycle starts.

    The diagram in the document is an exaggerated case where the PWM cycle is running at 47kHz and the ADC capture + FOC loop barely completes in time before the half cycle is over. A more relaxed case would be 20kHz or 32kHz PWM cycle so the ADC capture + FOC loop completes with time to spare in the half cycle. So, you would have a portion of that half cycle and the entire other half cycle to handle EtherCAT traffic or any other processing that you would like to do with your processor.

    Jason Reeder