Other Parts Discussed in Thread: AM6548
Dear TI Team,
we're using the EMIF configuration tool (AM65x/DRA80xM EMIF Tool Spreadsheet (ZIP 326 KB) 12 Oct 2018) to configure DDR controller settings for our custom AM6548 board.
So far we've noticed three (four) issues:
- The EMIF tool is unable to cope with comma as the decimal separator (e.g. german notation). What is problematic is that the tool "silently" fails in that case, and for example just calculates tRC=tRAS+tRP=35+13,75=35
- The EMIF tool puts "error" into certain register values if the C/A latency is specified as 4. The register values are fine if zero is used for c/a latency.
- A follow up to the previous issue: The tool apparently hard codes the C/A parity latency enable bit in DDRCTL_CRCPARCTL1 to 0.
- The EMIF tool is able to export a GEL file for use in CCS and a dtsi file for use in U-Boot but can't generate the necessary header file for the RTOS SDK SBL/board library.
We've managed to work around the first issue (after figuring out what's going wrong) by switching to a dot as the decimal separator in our Excel settings.
We believe we can ignore the second issue for now, since the third issue means that C/A parity is disabled anyway. Is that correct?
Our current issue is that our DDR settings "work" for when using them via the GEL file (not thoroughly tested) and as part of our SBL (at least a brief automated RAM test succeeds), but fails when using them as part of U-Boot (based on ti-u-boot-2018.01). So far we've noticed that the U-Boot DDR initialization fails during the call to read_dqs_training() since the QSGERR (DQS gate training error) bit gets set.
We're still in the process of verifying all of the timing settings, but your colleagues suggested to inform you about issues with the EMIF tool early on. It would also be nice to know if there are any further (known) issues with the EMIF tool.
Our setup uses a single 16 bit DDR4 memory chip (MT40A256M16).
Regards,
Dominic