RTOS/AM5728: MMU setting of using DDR-area(0xE000_0000) for PCIE data area

matusan

Guru 10235 points

Part Number: AM5728

Tool/software: TI-RTOS

Hello, TI Experts,

Our customer sent us question about MMU seting for PCIE with PROCESSOR-SDK-RTOS-AM57X.

They tried to add PCIE function to EcMaster product based on http://www.ti.com/lit/ug/tidubz1b/tidubz1b.pdf

They want to add MMU setting for PCIE(EP) data area (base address:0xE000_0000) in *.cfg file (EcMaster.cfg).

Question:

Could you tell us recommended MMU setting of using DDR-area(0xE000_0000) for PCIE data area including un-cache setting.

We' like to attach EcMaster.cfg as their project *.cfg file.

We would also appreciate if you check the MMU setting "EcMaster.cfg" and tell us how to modify this cfg file.

Best regards,

3618.EcMaster.cfg

over 5 years ago

0 lding over 5 years ago

TI__Guru* 95265 points

Hi,

Please refer to software-dl.ti.com/.../Mmu.html

SYS/BIOS assigns the following defaults to MAIR0 ATTR0, ATTR1 and ATTR2:
ATTR0 -> 0x44 (mark memory region as non-cacheable normal memory)
ATTR1 -> 0x00 (mark memory region as strongly ordered and non-cacheable)
ATTR2 -> 0xFF (mark memory region as normal memory, RW cacheable and
RW allocate)

If they want to DDR region starting from 0xE000_0000 as non-cacheable normal memory, they can use attribute index 0 for this. The cfg file needs an entry like:

Mmu.initDescAttrsMeta(attrs0);
attrs0.type = Mmu.DescriptorType_BLOCK; // BLOCK descriptor
attrs0.shareable = 2; // sharerable
attrs0.attrIndx = 0; // non-cached, normal memory

// Set the descriptor for each entry in the address range
for (var i=0xE0000000; i < 0x???????; i = i + 0x00200000) {
// Each 'BLOCK' descriptor entry spans a 2MB address range
Mmu.setSecondLevelDescMeta(i, i, attrs0);
}

Regards, Eric

0 matusan over 5 years ago in reply to lding

Guru 10235 points

Hi,

Thank you very much for your kindness.

I really appreciate your help.

I found attr0 setting in EcMaster.cfg (,which I attached on the previous post) like below.

>attrs0.attrIndx = 1;

So, I have one question.

Question:

Is it better to use new attrs such as attrs5 to prevent conflict of attrs0 setting like below?

var attrs5 = new Mmu.DescriptorAttrs();

Mmu.initDescAttrsMeta(attrs5);

attrs5.type = Mmu.DescriptorType_BLOCK; // BLOCK descriptor

attrs5.shareable = 2; // sharerable

attrs5.attrIndx = 5; // non-cached, normal memory

Mmu.setMAIRMeta(5, 0x44);

// Set the descriptor for each entry in the address range

for (var i=0xE0000000; i < 0x???????; i = i + 0x00200000) {

// Each 'BLOCK' descriptor entry spans a 2MB address range

Mmu.setSecondLevelDescMeta(i, i, attrs5);

}

Best regards,

0 lding over 5 years ago in reply to matusan

TI__Guru* 95265 points

Hi,

Yes, you can use a new one for this as you coded.

Regards, Eric

0 matusan over 5 years ago in reply to lding

Guru 10235 points

Hi,

Thank you very much for your kindness.

I really appreciate your help.

I will send the answer to the customer.

Best regards,

Processors

Processors forum

RTOS/AM5728: MMU setting of using DDR-area(0xE000_0000) for PCIE data area