AM3871: DDR3 design questions

1. Does it make sense in the gaps between the memory conductors of the 50th (3W), if the distance is reduced to the minimum allowable 0.1mm in the area of ​​the contact pads, at the points where the trails pass near the vias? (screenshot 50ohm.png)
2. What is the maximum difference in the lengths of the conductors between the groups BANK0, BANK1? Example: in my group the length of the conductors is aligned to 17mm, in the other to 31mm. Is this difference critical and do you need to align both groups to a certain average value?
3. In some documents, some processor manufacturers said that the maximum difference in length between DQS0 / DQS0 #, DQS1 / DQS1 #, DQS2 / DQS2 #, DQS3 / DQS3 and CK / CK # should be no more than 500mil. Is this requirement adequate and is compliance really necessary?

1. My ADDR_CMD / CK length is 46.75mm, which is 1840mil and it is more than 1250mil pipe length to use the minimum clearance. How critical in my case would be a 4mil gap, with a conductor width of 6.5mil (for Outer Layers) and 4.5 (for Inner Layers)? What is the optimal gap value for my situation (for outer and inner layers)?
2. Accepted
3. Accepted

I now have a gap value of 4mil for all layers.

My settings:
for Outer Layers: trace width 6,5mil
for Inner Layers: trace width 4,5mil

Question:
What is the value of the gap I choose to avoid problems with crosstalk?

I already use the minimum thickness of the dielectric for all layers. Core (construction: 2x (# 1506) 0.305mm), Prepreg (construction: 1x (# 106) 0.051mm). The width of the conductors with an impedance of 50 ohms and a tolerance of 10%. That is, do you still advise me to use 4mil clearance with the signal length group ADDR_CMD / CK 1840mil?

My PCB manufacturer does not have other materials available, or they are already significantly more expensive than standard FR-4 TG130.

I am sorry, I don't see how we can help with this. I am attaching a stackup that I have used, that needs 4.75mils on outer layers and 5.25mils on inner layers. Drill holes are 0.2mm with 16-20mils vias (I don't remember the exact via size).

Stackup.pdf

As far as I know, most manufacturers prohibit the use of 1 prepreg in the design of the board.

The design of the board often consists of:
2 prepreg
1 core
2 prepreg

With such a stack like yours, a high probability of manufacturing defects.You also use the expensive FR-4 material with a high glass transition temperature TG150-170 of the Dk value, the Df of which is usually lower than that of my TG130 material.

I am afraid only of crosstalk and therefore I do not know what kind of gap I should choose for my conductor widths.

First question:

Figure 9-60 (Rcp, Cac) , Figure 9-61 (Rtt)
In these figures, are these Rcp, Cac & Rtt components necessary only when using 4 memory modules? For two or less, this is not required?

Found an error:
Figure 9-58, Figure 9-59 - Lacked in the specification.

Second question:

8.2.9.2 Digital
Pay special attention not to put so much capacitance on the supply that it slows the start-up voltage ramp
enough to change the power sequencing order. Also be sure to verify that the main chip reset is low until
after all supplies are at their correct voltage and stable.

Table 9-71. Bulk Bypass Capacitors Per DDR3 EMIF
DDR_1V5 bulk bypass total capacitance 70 μF (min)

If I use TPS563200DDCT with 3 output filter capacitors of 22uF (66uF) to get 1V5, and also use 3x22uF as bulk capacitors as shown in table Table 9-71, will this violate the rule of section 8.2.9.2 Digital?

Biser, thank you for your replies. Please tell me.
Can I somehow, for example using a terminating serial resistor for example on the 50ohm, and having a conductor impedance of 75 ohm, reduce the conductor impedance to the 50ohm?

Please look at example:

Micron TN-41-13 (Figure 6 - Page 19)

Please explain what happens to the impedance when this resistor is installed? In TI documents, sometimes there are terminating resistors 0-22ohm on the ADDR / CTRL / CMD bus. Explain their meaning and how does their installation affect the conductor impedance?

Thank for your replies,

In some situations, it is required to separate Analog and Digital ground when using mixed signals. Based on what is written in the AM3871 specification, I see that this is not required.

1. I want to understand why this requirement does not apply to this processor? Explain, please.

I mean a similar scenario:

2. I noticed that the DDR_VREF pins, as well as some USB-bus pins, such as USB0_DP, USB0_DM and others, have an analog signal type (A). Why is it that way?

3. I cannot understand why a digital interface such as USB is marked in the documentation as an analog signal type (A)? Explain, please.

4. Does this mean that they require the presence of an analog ground plane under the tracks for return currents where these signals pass?

5. Is a solid reference plane needed for the power polygons on the inner layers? Does the gap in the plane on the adjacent inner layers if it intersects the polygon for example analog power on the adjacent inner layer?

Hello Biser,

I'm trying to choose a voltage regulator for DDR3 to generate VDDQ and I can’t understand what the optimal switching frequency should be in the case of dc-dc buck converter (step-down) and what it depends on. And shouldn't you use LDO instead of dc-dc buck converter for DDR3?