Tool/software: Code Composer Studio
Hi,
..this is on behalf of my customer...
We have a custom board based on TI’s Sitara AM3359 ICE V2 and we are trying to bring up the board in UART boot mode.
We are getting the “CCCC…” Prints on Uart 0 from the processor. When we try to load the “u-boot-spl.bin” file through x-modem from Uart, It shows the data transfer is successful. But we are not getting any prints of SPL after it is loaded (we have enabled “#define DEBUG” in the am335x_evm.h file). When we try to load the “u-boot.img” file through y-modem afterwards, we get “Transfer incomplete” message.
We have done the DDR initialization as per TI’s Guidelines using the Ratio-seed and DDR timing calculation .xlxs spread sheets provided by TI. We have modified the values in the GEL file by the values we got from the spread sheets and tested the DDR using JTAG and CCS8. DDR tests pass and We are able to read and write to the DDR location through memory browser from the CCS IDE. We have used the same values in the “ddr_defs.h” file and built the spl and u-boot files. Our DDR is the same as the one used in the Sitara Am3359 ICE v2 board.
I am attaching the Spread sheets and the GEL files along with the ddr_defs.h file used for building u-boot and u-boot-spl. Kindly help me in solving this issue as soon as possible.
Regards,
Muthu S
