TMS320C6670: the principles of caches

YaoTing Mao

Intellectual 540 points

Part Number: TMS320C6670

Hi all,

I have two questions about cache principle.

(1) from the document, DSP Cache User Guide, http://www.ti.com/lit/ug/sprugy8/sprugy8.pdf

If i put all of my program/data in L2 SRAM

page:1-13 shows L2 data/program needs to be fetched through L1, then CPU execute the code based on the program address in L2.

However, my colleague says he disables caches in L1 data(max L1 data SRAM) and disable SRAM in L1 program(max L1 program caches), so the situation should be CPU directly executes code in L2 and it doesn't matter if L1 has those data/program.

is this statement true?

(2) why we need two different layers, L1 and L2? Does CPU have different speed to fetch data/program in L1 and L2?

If they are the same, why not CPU directly access program and data in L2?

Thank you for response.

over 5 years ago

0 Yordan Kovachev over 5 years ago

TI__Guru**** 161600 points

Hi,

L2 provides an on-chip memory solution between the faster level 1 memories (L1D, L1P) and slower external memories. It is advantageous in that it supports larger memory sizes than the L1 memories, while providing faster access than external memories.
You should check also the C66x CorePac User's Guide (www.ti.com/.../sprugw0c.pdf).

As for why two layers L1 and L2 are needed, this is a general question on cpu architecture. I found quite good explanation about this here:
www.extremetech.com/.../188776-how-l1-and-l2-cpu-caches-work-and-why-theyre-an-essential-part-of-modern-chips

Best Regards,
Yordan

0 YaoTing Mao over 5 years ago in reply to Yordan Kovachev

Intellectual 540 points

Hi Yordan,
Thank you for the response.
i should specify my first question.
is it possible CPU can directly fetch code and data from L2 and skip L1 level?
Thanks

0 Yordan Kovachev over 5 years ago in reply to YaoTing Mao

TI__Guru**** 161600 points

Hi,

As per the C66x CorePack Users guide, you should go through L1 to access L2, I stated this above (L2 provides an on-chip memory solution between the faster level 1 memories (L1D, L1P) and slower external memories.) it is also stated in Figure 1-13 in the Cache User Guide. I haven't tested this personally (disable L1 and use L2 only), but also can't see the benefit of doing that.

Best Regards,
Yordan

0 Yordan Kovachev over 5 years ago in reply to Yordan Kovachev

TI__Guru**** 161600 points

Hi,

If you take a look at Chapter 5 C66x CorePac in the TMS320C6670 Data Manual you can see that there is direct access from the C66x CPU to the L2 through the UMC (unified memory controller). It is also stated (in the c66x dsp cache user guide) that: "If the data requested by the core is not contained in cache, it is fetched from the next lower memory level, L2 or external memory."
So when L1 cache is disabled the data should be fetched from L2 memory.

Best Regards,
Yordan

0 YaoTing Mao over 5 years ago in reply to Yordan Kovachev

Intellectual 540 points

Hi Yordan,

The unified memory controller doesn't say it directly pass data to CPU.

From cache user guide, page 1-10 figure 1-1, 1-13 figure 1-3, 1-15 figure 1-4, i will say unified memory controller pass L2 data to L1 cache, then CPU fetch the data.

it is impossible CPU can directly access L2/external memory without L1 caches.

Do you think my statement is reasonable?

Thanks.

0 YaoTing Mao over 4 years ago in reply to YaoTing Mao

Intellectual 540 points

Hi Yordan,

Do you have update to my previous post?

For your reference, I also find this document. https://e2echina.ti.com/cfs-file/__key/telligent-evolution-components-attachments/00-53-00-00-00-02-19-24/TMS320C6678_5F00_Memory_5F00_Access_5F00_Performance.pdf

in the page 6, figure 1. it shows L2 cannot directly be fetched by DSP core.

Thanks

0 Yordan Kovachev over 4 years ago in reply to YaoTing Mao

TI__Guru**** 161600 points

Hi,

From cache user guide, page 1-10 figure 1-1, 1-13 figure 1-3, 1-15 figure 1-4, i will say unified memory controller pass L2 data to L1 cache, then CPU fetch the data.

it is impossible CPU can directly access L2/external memory without L1 caches.

Yes, it seems the data path is through L1 caches.

As for the document you shared, I do not see it in the official documentation in TMS320C6670 Product Folder:
www.ti.com/.../technicaldocuments

Best Regards
Yordan

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TMS320C6670: the principles of caches