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TMS320C5515: Driving PLLIN with 1MHz

Bayan Oweida1
Prodigy 30 points
Part Number: TMS320C5515

Hello,

We have a system that divides the 12 MHz external oscillator by 12 before multiplying by 100 to generate the 100 MHz SYSCLK:

CGCR2 = 0x0008

CGCR1 = 0x9060

The output of the divider (1MHz) drives the Clock Generator PLL ( PLLIN in Figure 1-4 in sprufx5e.pdf).

However, the 1 MHz exceeds the PLLIN max of 170 KHz (Table 1-10 sprufx5e.pdf).

What are the implications of the above configuration on the device performance?

The board seems to work just fine.

Thanks

Bayan

  • 0
    TI__Guru**** 393215 points
    Hi,

    From what you post you have set bit 12 of CGCR1 to 1. This means that the PLL is powered down.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 30 points
    Thank you for your response,
    The PLL is powered down while changing the value to 8 (thus divide by 12) and to 96 (thus multiply by 100), as required.
    The PLL is subsequently powered up and a wait-time for the PLL to lock is allowed.
    Like I said, the 100 MHz is being generated and the board is working fine, or so it seems.
    Bayan
  • 0 in reply to Bayan Oweida1
    TI__Mastermind 29270 points
    Hi Bayan,

    1MHz CLKIN is outside of the supported range for PLLIN. Why don't you just pre-divide it with the RP[11:0] bit field?

    Utilize this PLL Calculator XLS Sheet to check for validity of the settings.
    processors.wiki.ti.com/.../C5505_PLL_Calculator_060210.zip

    Follow closely the PLL initialization sequence in the CSL library for this device: http://www.ti.com/tool/sprc133

    You can confirm that the SYSCLK is running at the desired frequency by enabling the CLKOUT signal:
    CPU ST3_55[0x0004@DATA]: CLKOFF bit (bit 2) - The CLKOUT pin is enabled/disabled When CLKOFF = 0, the CLKOUT pin is enabled; the associated clock signal appears on the pin. When CLKOFF = 1, the CLKOUT pin is disabled.

    The PLL might be in bypass mode, so enabling the CLKOUT is a valuable debug tool.

    Hope this helps,
    Mark
  • 0 in reply to Mark Mckeown
    Prodigy 30 points
    Hi Mark and thank you for your response
    I know that the PLL is running and is generating the 100 MHz. We plan to change the design and make sure that the input to the PLL is within spec. Unfortunately we have boards (working) with the input to the PLL set at 1 MHz. We would like to assess the impact of the PLL, running outside its range, on the device performance. We are bothered by the fact that the PLL is running while its input is outside the specified range.
    Thanks again,
    Bayan
  • 0 in reply to Bayan Oweida1
    TI__Mastermind 29270 points
    Hello Bayan,

    I understand now. I have asked one of our analog designers if he can speculate what the impact of operating the PLLIN out of spec will be.

    I can confirm we did not test the PLL with 1MHz PLLIN. The C5515 PLL is an analog PLL. I might expect some issue with either the phase detector or the loop filter pass band, but it is difficult for me to say. Lets hope the analog designer can offer more impact analysis.

    Refer to this APLL tutorial: www.electronics-notes.com/.../tutorial-primer-basics.php

    Regards,
    Mark
  • 0 in reply to Mark Mckeown
    TI__Mastermind 29270 points
    Hi Bayan,

    I'm sorry. I never did hear back from the designer about this issue. I expect his answer would have been academic anyway since we cannot recommend a PLLIN > 170kHz. I'm going to close this thread. I apologize that we could not provide an impact analysis for the 1MHz PLLIN scenario.

    Regards,
    Mark