Hi,
Is it possible to ensure the real time capability while PRU-ICSS accesses the resource on L3/L4?
Though TI has provided a reference design about the SPI firmware on PRU (http://www.ti.com/tool/TIDEP0033),
it is an assembly code and a little hard for further development and integration. So, I want to access L3/L4 resource
on PRU-ICSS, but it also means the data path is longer than before and the latency might be non deterministic
due to bus conflict, right?
