TDA3MV: TDA3 DDR3 timing simulation

Peter Hesseltun

Part Number: TDA3MV

Hi, I would like to perform some timing simulation on the DDR3 interface on the TDA3 SoC but there's no info about setup/hold times etc in the data sheet.
In the datasheet there's only length constraints. Is it possible to get some timing information for this interface?

BR
Peter

over 4 years ago

0 Rishabh Garg over 4 years ago

TI__Guru 55685 points

Hi,

You need to refer to EMIF tools: http://www.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=sprac36

Regards,

Rishabh

0 Kevin S over 4 years ago

TI__Mastermind 26595 points

Hi,

In addition to following the layout and routing guidelines documented in the datasheet, we recommend that customer simulations focus on skew minimization and signal integrity.

Best regards,
Kevin

0 Peter Hesseltun over 4 years ago in reply to Rishabh Garg

Prodigy 20 points

I'm looking for information about:

tADCMSU, tADCMHL, tCKDQS, tDS and tDH

and I couldn't find those numbers there.

/Peter

0 Kevin S over 4 years ago in reply to Peter Hesseltun

TI__Mastermind 26595 points

Hi Peter,

You are correct that the datasheet does not provide DDR timing information.

TI’s support model for the TDA3x EMIF/DDR interface is to solve the complex timing and signal integrity challenges for our customers and translate them into DDR PCB routing requirements that are documented in the device data manuals. In addition, TI IBIS models should be used to verify signal integrity; however, we do not recommend or support using IBIS models for overall interface timing studies.

Best regards,
Kevin

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TDA3MV: TDA3 DDR3 timing simulation