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Part Number: TDA3MV
Hi, I would like to perform some timing simulation on the DDR3 interface on the TDA3 SoC but there's no info about setup/hold times etc in the data sheet.In the datasheet there's only length constraints. Is it possible to get some timing information for this interface?
You need to refer to EMIF tools: http://www.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=sprac36
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In addition to following the layout and routing guidelines documented in the datasheet, we recommend that customer simulations focus on skew minimization and signal integrity.
In reply to Rishabh Garg:
I'm looking for information about:
tADCMSU, tADCMHL, tCKDQS, tDS and tDH
and I couldn't find those numbers there.
In reply to Peter Hesseltun:
You are correct that the datasheet does not provide DDR timing information.
TI’s support model for the TDA3x EMIF/DDR interface is to solve the complex timing and signal integrity challenges for our customers and translate them into DDR PCB routing requirements that are documented in the device data manuals. In addition, TI IBIS models should be used to verify signal integrity; however, we do not recommend or support using IBIS models for overall interface timing studies.
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