OMAP-L138: Schematic Review

Hi ikon,

The connections with the DNA components not populated look good for using an external clock oscillator. I would not recommend populating the components to use the external crystal (X3116) due to the noise immunity issue with the OSCIN input (as documented in the errata).

SiT5356 meets rise/fall recommendation from errata 1.9ns max rise/fall < 5ns (see errata)
SiT5356 meets pulse width requirements 0.45*tC > 0.40*tC (see datasheet Table 6-3)
SiT5356 meets rise fall requirement (1.9ns / (1/24MHz)) < (0.25P or 10)

I would recommend modifying the resistor divider network so that the OSCIN amplitude is greater. OSCIN amplitude needs to satisfy VIL/VIH requirements relative to CVDD:
    OSCIN Voltage Input High = 0.8 * CVDD
    OSCIN Voltage Input Low = 0.2 * CVDD

What is the CVDD voltage?

Calculating worst case for 1% tolerant resistors and worst case Output Voltage High from SiT5356 (0.9 * VDD) with VDD = 3.3V exactly, the OSCIN high amplitude might be 0.925V at the OSCIN pin. This satisfies the OSCIN VIH requirement only when CVDD = 1.0V. A greater OSCIN VIH is required if CVDD = 1.1V, 1.2V, or 1.3V.

I did not check VIL.

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For added ESD noise immunity, follow the layout routing recommendations from the Errata including these that I have highlighted...

* OSCIN and OSCVSS (and OSCOUT, if used) should be routed as short as possible on inner board layers where it is shield by power and ground planes

* The processor should be provided as much power supply decoupling as is practical and placed as
close to the processor as possible.

* Utilize PLL filtering circuits

The customer might also contact SiTime for better EMI performance from the SiT5356. See this note in their datasheet:
SiT5356AC-FQ-33N0-24.000000 the first “-“ corresponds to the default rise/fall time for LVCMOS output as specified in Table 1 (Electrical Characteristics). Contact SiTime for other rise/fall time options for best EMI

Regards,
Mark