Other Parts Discussed in Thread: AMIC110, , AMIC120
I have questions about data path setup in MII_RT of AMIC110 PRU-ICSS. (TRM 4.4.6.2.1 Data Path Configuration)
When using full duplex communication
- Frames received on one port are sent to the other
- AMIC 110 may also transmit data
For this reason, I am trying to switch the following as needed.
- Normally wait in "Auto-forward" to reduce the delay time.
- When sending by yourself "32-byte Double Buffer or Ping-Pong Processing"
However, because the switching timing is bad, the output Ethernet frame is it may be broken and it takes time to adjust.
It could be the switching timing of the above two, but there are cases that Ethernet frame output is corrupted and I'm struggling to adjust it and fix the problem.
To confirm that my approach is correct or not, I have following questions. I'm using TMDXICE110.
1.
Whether MII_RT is receiving Ethernet frames or not, TXCFG register TX_AUTO_SEQUENCE seems to be reflected. Is this correct?
If so, I think it is necessary to avoid the receiving state in order not to break the flowing frame.
As a way to do so, I'm thinking about changing settings after confirming that "RX_SOF is not detected in INTC". Can this be in time ?
Would it be no data flow to the TX FIFO while changing TX_AUTO_SEQUENCE to disable?
2.
When resetting the receive FIFO by RX_RESET, are both RX L1 FIFO and RX L2 FIFO cleared even if TX_AUTO_SEQUENCE is enable ?
3.
If you change TX_AUTO_SEQUENCE from enable to disable, I do not think I can't find how much data is in TX L1 FIFO. Is this correct?
4.
When transmitting, I'm using CRC32 calculation function of MII_RT (cmdR31 [TX_CRC_HIGH + TX_CRC_LOW + TX_EOF]).
Before switching TX_AUTO_SEQUENCE from disable to enable, do I have to wait for several clocks or until the TX L1 FIFO is empty?
