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PROCESSOR-SDK-AM57X: 128MB QSPI flash support in RTOS

Part Number: PROCESSOR-SDK-AM57X

Dear Champs,

My customer is using RTOS PSDK 5.3 now, and want to check if 128MB qspi flash memory can be used.

As I know, only 16MB can be supported at boot time, and 64MB can be supported in the TI-RTOS after booting, right?

The target qspi flash memory is S70FL01GS with 128MB size and there are 2 CS pins to access full 128MB region as below.

could you please let me know if this CS pin can be controlled in the TI-RTOS qspi driver?

is there any way to access full 128MB regions of qspi flash memory with CS pin control?

Thanks and Best Regards,

SI.

  • SI, 

    I am not sure what is the dependence on Processor SDK RTOS here. We provide a QSPI driver and a higher level flash API that can handle three byte address and 4 byte addressing mode with each chip select.  This means that we have 64 MB supported on CS0 of the QSPI which is what we support on AM57x IDK configuration.

    This can be extended to 128 MB if the customer configuration uses two chip selects. The default ChipSelect for the SOC configured in the SPI driver configuration is 0 so the customer application code may need to create two handles for different chip selects or close one handle and open another when the flash write address is greater then 64 MB. The higher flash address provided from application needs to be translated to flash memory address of flash on the second chip select. as each chip address will range upto 64MB.

    The default QSPI init CFG is provided in the SPI_soc.c file in the folder pdk_am57xx_1_0_13\packages\ti\drv\spi\soc\am572x\SPI_soc.c

    /* SPI configuration structure */
    QSPI_HwAttrs qspiInitCfg[CSL_QSPI_PER_CNT] =
    {
        {
            CSL_MPU_QSPI_ADDRSP0_REGS,  /* register baseAddr */
            CSL_MPU_QSPI_ADDRSP1_REGS,  /* memMappedBaseAddr */
            48000000,               /*Input frequency */
    #ifdef _TMS320C6X
            15U,
    #elif defined(__ARM_ARCH_7A__)
            67U,                    /* 35 + 32 */
    #else
            62U,
    #endif
    #ifdef _TMS320C6X
            38U, /*343U,*/
    #elif defined(__ARM_ARCH_7A__)
            35U, /*343U,*/
    #else
            0U,  /*343U,*/
    #endif
            QSPI_OPER_MODE_MMAP,            /* operMode */
            0U,                            /* chipSelect */
            QSPI_CS_POL_ACTIVE_LOW,        /* csPol */
            QSPI_CLK_MODE_3,               /* frmFmt */
            QSPI_DATA_DELAY_0,             /* dataDelay */
            QSPI_RX_LINES_QUAD,          /* rxLines */
            true,
        }
    };

    Hope this  helps out your customer in how to handle the 128 MB QSPI interface.

    Regards,

    Rahul