TMS320C6657: Schematic doubt

Hi Nancy,

You can check the acceptable values of DDRCLK from the Datasheet, Table 5-7. DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements and the Hardware Design Guide, Table 6. KeyStone I System PLL Clock Inputs.

However in TMS320C6657 design I think there is a typo and the clock should be 66.67MHz, based on the fact that TMS320C6678 & TMS320C6657 EVMs have similar design, and TMS320C6678 EVM uses 66.67MHz for DDRCLKP/N. Also if you check Figure 16. Clock Fan Out - Multiple DSPs, which shows the recommended clock source as applied to multiple DSPs using alternate TI clock sources (CDCL6010 and CDCE62005), you will see that if you have 25MHz XTAL connected to CDCE62005, the DDRCLKP/N is 66.67MHz.

Best Regards,
Yordan