AM1806: How to configure to decrease the negated period of EMA_CS2?

Hello HaTa,

This issue was discussed in the following thread: https://e2e.ti.com/support/processors/f/791/p/265264/928200#928200

This has to do with data transfer latencies through the system interconnect. Read transactions are usually more costly (in clock cycles) than writes. For writes, the command and data flow together and can be thought of as "fire-and-forget" in nature. Once a write transaction leaves the master/initiator boundary (ex: sitting in a bridge or an end point's buffer or FIFO), the initiator can proceed to the next write (even before the previous write reaches its final destination). For reads, a read command pends until a read response/data returns. So in general, the initiator cannot issue a new read/write command until the previous read command's response reaches the master/initiator.

You may want to take a close look at the information in the wiki page below and linked pages to gain a better understanding of the data transfer through the interconnect:

http://processors.wiki.ti.com/index.php/OMAP-L1x/C674x/AM1x_SOC_Architecture_and_Throughput_Overview

If you have any questions please let me know.

Regards,
Sahin

Hi HaTa,

HaTa said:

  - Change the priority of SCR (Switch Central resources) for ARM to higher one

• The SCR allows for concurrent transactions to be passed through at the same time as long as the master/slave pair is unique. So this would only be beneficial if arbitration is occurring which only happens if another master is attempting to access the EMIFA at the same time as the ARM. For your simple test application this wouldn't help, but in a larger application with other masters this could improve latency. 

• The turnaround time (TA field in CEnCFG register) can typically be tuned to reduce latency between reads.
  
  EDIT: Given CE2CFG=0x00720301, the turnaround time is already configured at the lowest possible setting.
  
  
• Another thing that should improve performance is to enable cache if not enabled already. This will allow for an entire "burst" of the cache line, as the EMIFA has a dedicated port to the CPU's program cache. 
  
  
• Is increasing the EMIFA clock an option? The table below shows the supported frequencies for the EMIFA and the required DIV settings.
  
• Another option is to use the EDMA for larger bursts of data. I'm not sure if this will reduce the latency seen between reads, but it should at least reduce the frequency at which the delay occurs.

I hope this helps.

Regards,
Sahin