So,
I'm bolting an external 16-bit device to the GPMC, in NOR mode, A/D multiplexed. I understand that the AM335x is Little-Endian. I also understand how Endian-ness affects the order of bytes stored in memory, as I've worked with both architectures. Just so I'm completely clear for the AM3354, I'd like some clarification of how the GPMC presents data externally for 16-bit accesses.
1) When doing a 16-bit aligned write to the GPMC (A[0]=0) does D[15:0] represent memory byte order or does it represent a 16-bit word? That is, will a 16 bit value of 0x55AA have 0x55 on GPMC_AD[15:8] or GPMC_AD[7:0]?
2) When doing a 32-bit write to the GPMC, section 7.1.2.3.8.2.2 of SPRUH73P says "System requests with data width data greater than the external device data bus width are split into successive accesses according to both the external data-bus width and little-endian data organization." I'm aware that in AD-Multiplexed mode A[1] is on AD[0]. Does this mean that a 32-bit write D[31:0] will be written in D[15:0] with A[1] = 0, then D[31:16] with A[1] = 1?
Thanks
-Paul
