DRA718: HW leveling issue

Raul Matos

Part Number: DRA718
Other Parts Discussed in Thread: DRA71

Posting on behalf of my customer:

We need to reopen a thread from 2018 about HW leveling using DRA71 (EMIF1) + 2 * memory DDR3 IM4G16D3FABG-125I @ 666 [MHz].
Summarizing, we found an issue when enabling hw leveling. SPL gets stuck after mem alloc. Using SW leveling goes OK, but some boards has memory errors (some bits toggles to 1 and others to 0 randomly) maybe because they are outside operation performance range, that's the reason why we need to try enabling hw leveling.
Read DQS Gate and Read data eye training are failing. This was done calculating HW leveling and then copying SW leveling calculated values to regs corresponding only to Write leveling. Specifically found failed Data Macro 0 and DM3 at Read DQS Gate Training and failed DM1, DM2, and DM3 Read data eye training.
Regs calculated using EMIF tool by HW leveling are:

EMIF_EXT_PHY_CONTROL_2: 0x70000e7

EMIF_EXT_PHY_CONTROL_3: 0x7000080

EMIF_EXT_PHY_CONTROL_4: 0x700007d

EMIF_EXT_PHY_CONTROL_5: 0x70000fb

EMIF_EXT_PHY_CONTROL_6: 0x7000082

EMIF_EXT_PHY_CONTROL_7: 0x7f

EMIF_EXT_PHY_CONTROL_8: 0x4a

EMIF_EXT_PHY_CONTROL_9: 0x4a

EMIF_EXT_PHY_CONTROL_10: 0x1f

EMIF_EXT_PHY_CONTROL_11: 0x7f

EMIF_EXT_PHY_CONTROL_12: 0x4d004e

EMIF_EXT_PHY_CONTROL_13: 0x11005f

EMIF_EXT_PHY_CONTROL_14: 0x2190070

EMIF_EXT_PHY_CONTROL_15: 0x86006b

EMIF_EXT_PHY_CONTROL_16: 0x6b0080

EMIF_EXT_PHY_CONTROL_17: 0x2d002e

EMIF_EXT_PHY_CONTROL_18: 0x3f1003f

EMIF_EXT_PHY_CONTROL_19: 0x1f90050

EMIF_EXT_PHY_CONTROL_20: 0x66004b

EMIF_EXT_PHY_CONTROL_21: 0x4b0060

Any help would be much appreciated and please let me know if you need more information.

over 4 years ago

0 Kevin S over 4 years ago

TI__Mastermind 26735 points

Hi Raul,

"Regs calculated using EMIF tool by HW leveling are:"

Is this stating that the XLS generated these values? Or are these the values read back from silicon after executing hardware leveling?

Can you send me a private message with the customer's filled out XLS spreadsheet for their system?

Best regards,
Kevin

0 Pablo D'Angelo over 4 years ago in reply to Kevin S

Prodigy 40 points

Hello Kevin,
I'm part of this proyect. There is an error, it must say "Regs calculated by HW leveling are:".
Giving more information, this are some registers used (note that no leveling training is masked):

.emif_ddr_phy_ctlr_1_init = 0x0024400E,
.emif_ddr_phy_ctlr_1 = 0x0E24400E,

Best regards,
Pablo

0 Raul Matos over 4 years ago in reply to Pablo D'Angelo

TI__Expert 5125 points

To complement Pablo's:

Indeed XLS's value is .emif_ddr_phy_ctlr_1_init = 0x0824400E, but we changed it to 0x0024400E to enable Read data eye training and perform a full leveling. What's the reason to disable Read data eye training?
We have tested about 8 boards all with this fail in Read data eye training and only one of them also fails at Read DQS Gate training. Our spreadsheet (date: 2017/03/28) has calculated values according to our board trace lengths (not default TI EVM). The newer XLS version (date: 2018/11/29) gives same values in all regs except this one: .emif_ddr_phy_ctlr_1_init = 0x0024400E (enables all trainings).

0 Kevin S over 4 years ago in reply to Raul Matos

TI__Mastermind 26735 points

Hi Pablo,

>> There is an error, it must say "Regs calculated by HW leveling are:".

I apologize, but I am not sure I understand. Can you provide more details as to what indicates an error?

Hi Raul,

>> Our spreadsheet (date: 2017/03/28) has calculated values according to our board trace lengths (not default TI EVM).

The spreadsheet that was forwarded appears to have the exact same trace length values that the XLS defaults to. Is it possible that the incorrect XLS was provided? Regardless, did we try zeroing out registers PHY_26 - PHY_35 in the software configuration (being applied to the registers before the initialization / training)?

>>The newer XLS version (date: 2018/11/29) gives same values in all regs except this one: .emif_ddr_phy_ctlr_1_init = 0x0024400E (enables all trainings).

Can you double check that the part number was changed to DRA71x in the System Details tab? The XLS tool does not enable read data eye training for DRA71x.

Thanks,
Kevin

0 Brad Griffis over 4 years ago in reply to Kevin S

TI__Guru*** 125430 points

Pablo,

I have some scripts for Code Composer Studio that can help us quickly analyze your system. The general process for running these scripts is described here:

http://git.ti.com/sitara-dss-files/am57xx-dss-files/blobs/master/README

The specific script you should download and run is this one:

http://git.ti.com/sitara-dss-files/am57xx-dss-files/blobs/raw/master/am57xx-ddr.dss

After opening it in the browser you can click Ctrl-S to save it. Be careful about the file extension when you save it. A lot of web browsers add *.txt to it unnecessarily.

In short, we'd like to scrape the device registers using the am57xx-ddr.dss script above, and then compare those values against the spreadsheet to confirm everything matches as expected. There's a section in the spreadsheet where you enter trace lengths for CLK and DQS pins. Have you filled that out? Correspondingly it generates a structure of PHY_CONTROL values. Are those values leveraged in u-boot? Some of the past failures I've seen with hardware leveling have been a result of not properly leveraging those values.

Please attach the DSS output and your completed spreadsheet to this thread for further analysis.

Best regards,
Brad

0 Pablo D'Angelo over 4 years ago in reply to Brad Griffis

Prodigy 40 points

Hi Kevin, Brad,
Thanks for your replies. I will resume all the info to avoid any confusion.
- We are using DRA71 (EMIF1) + 2 * memory DDR3 IM4G16D3FABG-125I @ 666 [MHz].
- When enabling Read DQS Gate training and Write training in HW leveling, SPL gets stuck after a mem alloc because of Read DQS Gate training. (in another test enabling Read data eye training and Write training in HW leveling we found Read data eye training is also failing).
- Using SW leveling for all trainings goes OK.

After your replies we try zeroing out registers from EMIF1_EXT_PHY_CTRL_26 to EMIF1_EXT_PHY_CTRL_35 and only masking read data eye training (.emif_ddr_phy_ctlr_1_init = 0x0824400E), and now it works!
After all this, some questions comes up:
1) Is not read data eye training implemented for DRA71x? So it's ok to mask it?
2) Filling PHY_26 to 35 with zeros is a fast fix. What would be a correct fix? Would this mean the calculated trace lengths are incorrect?

EMIF tool Used values - Sheet "Step2-BoardDetails": trace length for our specific board:

DRAMs Connected to EMIF1, Rank 0
DRAMs Connected to EMIF1, Rank 0
Signal	PCB Trace Length in MILs (1/1000 inch)
	Byte 0		Byte 1		Byte 2		Byte 3		ECC
	Microstrip	Stripline	Microstrip	Stripline	Microstrip	Stripline	Microstrip	Stripline	Microstrip	Stripline
CLK	3357.87	373	3357.87	373	3357.87	959.08	3357.87	959.08	3357.87	1557.31
DQSn	2156.8	0	2143.34	0	1887.73	0	1898.17	0	1491.53	0

Attached files using brad's script for Code Composer Studio:
- am57xx-ddr_2019-11-21_165341.txt: with PHY_26 to 35 calculated from EMIF tool and only read data eye training masked. Gets stuck.
- am57xx-ddr_2019-11-21_165603_zeroed.txt: with PHY_26 to 35 zeroed and only read data eye training masked. Works OK.

Best regards,
Pablo

am57xx-ddr_2019-11-21_165341.txt

********************** DPLL_DDR **********************

CTRL_CORE_BOOTSTRAP = 0x00000320
  * SPEEDSELECT = 19.2 MHz
CM_CLKSEL_DPLL_DDR = 0x00022b07
  * DPLL_MULT = 555 (x555)
  * DPLL_DIV = 7 (/8)
CM_DIV_M2_DPLL_DDR = 0x00000202
  * CLKST = 1: M2 output clock enabled
  * DIVHS = 2 (/2)
CM_DIV_H11_DPLL_DDR = 0x00000208
  * CLKST = 1: H11 output clock enabled
  * DIVHS = 8 (/8)

DPLL_DDR Summary
 -> F_input = 19.2 MHz
 -> F_dpll_ddr = 2664 MHz
 -> CLKOUT_M2 = EMIF_PHY_GCLK = 666 MHz
 -> CLKOUTX2_H11 = EMIF_DLL_GCLK = 333 MHz

********************** DMM - LISA **********************

DMM_LISA_MAP_0 = 0x00000000
DMM_LISA_MAP_1 = 0x00000000
DMM_LISA_MAP_2 = 0x80600100
  * System Address Mapping = 0x80000000
  * Section Size = 1024 MB
  * Mapped to EMIF1
DMM_LISA_MAP_3 = 0xff020100
  * System Address Mapping = 0xff000000
  * Section Size = 16 MB
  * Mapped to EMIF1

********************** EMIF1 **********************

CTRL_CORE_CONTROL_DDRCACH1_0 = 0x60606060
ddr1_casn, ddr1_rasn, ddr1_rst, ddr1_wen, ddr1_csn[0], ddr1_cke, ddr1_odt[0]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 40 Ohms
ddr1_a[15:0]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 40 Ohms
ddr1_ba[0], ddr1_ba[1], ddr1_ba[2]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 40 Ohms
ddr1_ck, ddr1_nck
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 40 Ohms

CTRL_CORE_CONTROL_DDRCH1_0 = 0x40404040
ddr1_d[7:0], ddr1_dqm[0]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[0], ddr1_dqsn[0]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_d[15:8], ddr1_dqm[1]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[1], ddr1_dqsn[1]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH1_1 = 0x40404040
ddr1_d[23:16], ddr1_dqm[2]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[2], ddr1_dqsn[2]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_d[31:24], ddr1_dqm[3]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[3], ddr1_dqsn[3]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH1_2 = 0x00404000
ddr1_ecc_d[7:0], ddr1_dqm_ecc
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs_ecc, ddr1_dqsn_ecc
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRIO_0 = 0x00094a40
ddr1_d[7:0], ddr1_d[15:8]
  * Internal VREF disabled
ddr1_d[23:16], ddr1_d[31:24], ddr1_ecc_d[7:0]
  * Internal VREF disabled

CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT = 0x0001c1a7
  * Bit 16: EMIF1_EN_ECC = 1
EMIF_ECC_CTRL_REG = 0x00000000
  * Bit 31: reg_ecc_en = 0
  * Bit 30: reg_ecc_addr_rgn_prot = 0
  * Bit 29: reg_ecc_verify_dis = 0, enable ECC verification on reads (normal)
  * Bit 1: reg_ecc_addr_rgn_2_en = 0
  * Bit 0: reg_ecc_addr_rgn_1_en = 0
EMIF_ECC_ADDRESS_RANGE_1 = 0x00000000
EMIF_ECC_ADDRESS_RANGE_2 = 0x00000000
EMIF_1B_ECC_ERR_CNT = 0x00000000
EMIF_1B_ECC_ERR_THRSH = 0x00000000
EMIF_1B_ECC_ERR_DIST_1 = 0x00000000
EMIF_1B_ECC_ERR_DIST_1 = 0x00000000
EMIF_2B_ECC_ERR_ADDR_LOG = 0x00000000
EMIF_STATUS = 0x40000004

EMIF_SDRAM_CONFIG = 0x61822b32
EMIF_SDRAM_CONFIG_2 = 0x00000000
EMIF_SDRAM_REFRESH_CONTROL = 0x10001453
EMIF_SDRAM_TIMING_1 = 0xd113983c
EMIF_SDRAM_TIMING_2 = 0x31007fe3
EMIF_SDRAM_TIMING_3 = 0x40bf8f38
EMIF_READ_WRITE_LEVELING_RAMP_WINDOW = 0x00000000
EMIF_READ_WRITE_LEVELING_RAMP_CONTROL = 0x00000000
EMIF_READ_WRITE_LEVELING_CONTROL = 0x00000000
EMIF_DDR_PHY_CONTROL_1 = 0x0e24400e
  * Bits 4:0 READ_LATENCY = 14
  * Bit 9 PHY_FAST_DLL_LOCK = 0
  * Bits 17:10 PHY_DLL_LOCK_DIFF = 16
  * Bit 18 PHY_INVERT_CLKOUT = 1
  * Bit 19 PHY_DIS_CALIB_RST = 0
  * Bit 20 PHY_CLK_STALL_LEVEL = 0
  * Bit 21 PHY_HALF_DELAYS = 1
  * Bit 25 WRLVL_MASK = 1
  * Bit 26 RDLVLGATE_MASK = 1
  * Bit 27 RDLVL_MASK = 1

EMIF_EXT_PHY_CONTROL_1  = 0x04040100
EMIF_EXT_PHY_CONTROL_2  = 0x000000ea
EMIF_EXT_PHY_CONTROL_3  = 0x000000fd
EMIF_EXT_PHY_CONTROL_4  = 0x00000000
EMIF_EXT_PHY_CONTROL_5  = 0x000000fc
EMIF_EXT_PHY_CONTROL_6  = 0x00000089
EMIF_EXT_PHY_CONTROL_7  = 0x002f002f
EMIF_EXT_PHY_CONTROL_8  = 0x002f002f
EMIF_EXT_PHY_CONTROL_9  = 0x002f002f
EMIF_EXT_PHY_CONTROL_10 = 0x002f002f
EMIF_EXT_PHY_CONTROL_11 = 0x002f002f
EMIF_EXT_PHY_CONTROL_12 = 0x00930053
EMIF_EXT_PHY_CONTROL_13 = 0x02430061
EMIF_EXT_PHY_CONTROL_14 = 0x03120075
EMIF_EXT_PHY_CONTROL_15 = 0x03ad006d
EMIF_EXT_PHY_CONTROL_16 = 0x02de008a
EMIF_EXT_PHY_CONTROL_17 = 0x00730033
EMIF_EXT_PHY_CONTROL_18 = 0x02230041
EMIF_EXT_PHY_CONTROL_19 = 0x02f20055
EMIF_EXT_PHY_CONTROL_20 = 0x038d004d
EMIF_EXT_PHY_CONTROL_21 = 0x02be006a
EMIF_EXT_PHY_CONTROL_22 = 0x00800080
EMIF_EXT_PHY_CONTROL_23 = 0x00800080
EMIF_EXT_PHY_CONTROL_24 = 0x40010080
EMIF_EXT_PHY_CONTROL_25 = 0x08102040
EMIF_EXT_PHY_CONTROL_26 = 0x005b00a0
EMIF_EXT_PHY_CONTROL_27 = 0x005b00a0
EMIF_EXT_PHY_CONTROL_28 = 0x005b00a5
EMIF_EXT_PHY_CONTROL_29 = 0x005b00a6
EMIF_EXT_PHY_CONTROL_30 = 0x005b00a9
EMIF_EXT_PHY_CONTROL_31 = 0x00300043
EMIF_EXT_PHY_CONTROL_32 = 0x00300043
EMIF_EXT_PHY_CONTROL_33 = 0x0030004f
EMIF_EXT_PHY_CONTROL_34 = 0x0030004f
EMIF_EXT_PHY_CONTROL_35 = 0x0030005c
EMIF_EXT_PHY_CONTROL_36 = 0x00000077

EMIF_EXT_PHY_STATUS_1  = 0x001141f3
EMIF_EXT_PHY_STATUS_2  = 0xac462d15
EMIF_EXT_PHY_STATUS_3  = 0x60001138
EMIF_EXT_PHY_STATUS_4  = 0x00020000
EMIF_EXT_PHY_STATUS_5  = 0x00099999
EMIF_EXT_PHY_STATUS_6  = 0x00001924
EMIF_EXT_PHY_STATUS_7  = 0x00000000
EMIF_EXT_PHY_STATUS_8  = 0x00000000
EMIF_EXT_PHY_STATUS_9  = 0x00000000
EMIF_EXT_PHY_STATUS_10 = 0x00000000
EMIF_EXT_PHY_STATUS_11 = 0x00000000
EMIF_EXT_PHY_STATUS_12 = 0x070000ea
EMIF_EXT_PHY_STATUS_13 = 0x070000fd
EMIF_EXT_PHY_STATUS_14 = 0x07000100
EMIF_EXT_PHY_STATUS_15 = 0x070000fc
EMIF_EXT_PHY_STATUS_16 = 0x07000089
EMIF_EXT_PHY_STATUS_17 = 0x00930053
EMIF_EXT_PHY_STATUS_18 = 0x02430061
EMIF_EXT_PHY_STATUS_19 = 0x02230041
EMIF_EXT_PHY_STATUS_20 = 0x03ad006d
EMIF_EXT_PHY_STATUS_21 = 0x02de008a
EMIF_EXT_PHY_STATUS_22 = 0x00730033
EMIF_EXT_PHY_STATUS_23 = 0x02230041
EMIF_EXT_PHY_STATUS_24 = 0x02f20055
EMIF_EXT_PHY_STATUS_25 = 0x038d004d
EMIF_EXT_PHY_STATUS_26 = 0x02be006a
EMIF_EXT_PHY_STATUS_27 = 0x11ff3422
EMIF_EXT_PHY_STATUS_28 = 0x0000000f

am57xx-ddr_2019-11-21_165603_zeroed.txt

********************** DPLL_DDR **********************

CTRL_CORE_BOOTSTRAP = 0x00000320
  * SPEEDSELECT = 19.2 MHz
CM_CLKSEL_DPLL_DDR = 0x00022b07
  * DPLL_MULT = 555 (x555)
  * DPLL_DIV = 7 (/8)
CM_DIV_M2_DPLL_DDR = 0x00000202
  * CLKST = 1: M2 output clock enabled
  * DIVHS = 2 (/2)
CM_DIV_H11_DPLL_DDR = 0x00000208
  * CLKST = 1: H11 output clock enabled
  * DIVHS = 8 (/8)

DPLL_DDR Summary
 -> F_input = 19.2 MHz
 -> F_dpll_ddr = 2664 MHz
 -> CLKOUT_M2 = EMIF_PHY_GCLK = 666 MHz
 -> CLKOUTX2_H11 = EMIF_DLL_GCLK = 333 MHz

********************** DMM - LISA **********************

DMM_LISA_MAP_0 = 0x00000000
DMM_LISA_MAP_1 = 0x00000000
DMM_LISA_MAP_2 = 0x80600100
  * System Address Mapping = 0x80000000
  * Section Size = 1024 MB
  * Mapped to EMIF1
DMM_LISA_MAP_3 = 0xff020100
  * System Address Mapping = 0xff000000
  * Section Size = 16 MB
  * Mapped to EMIF1

********************** EMIF1 **********************

CTRL_CORE_CONTROL_DDRCACH1_0 = 0x60606060
ddr1_casn, ddr1_rasn, ddr1_rst, ddr1_wen, ddr1_csn[0], ddr1_cke, ddr1_odt[0]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 40 Ohms
ddr1_a[15:0]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 40 Ohms
ddr1_ba[0], ddr1_ba[1], ddr1_ba[2]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 40 Ohms
ddr1_ck, ddr1_nck
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 40 Ohms

CTRL_CORE_CONTROL_DDRCH1_0 = 0x40404040
ddr1_d[7:0], ddr1_dqm[0]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[0], ddr1_dqsn[0]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_d[15:8], ddr1_dqm[1]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[1], ddr1_dqsn[1]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH1_1 = 0x40404040
ddr1_d[23:16], ddr1_dqm[2]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[2], ddr1_dqsn[2]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_d[31:24], ddr1_dqm[3]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs[3], ddr1_dqsn[3]
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRCH1_2 = 0x00404000
ddr1_ecc_d[7:0], ddr1_dqm_ecc
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms
ddr1_dqs_ecc, ddr1_dqsn_ecc
  * Pull logic is disabled
  * Slew rate is 0, where 0=fastest and 7=slowest
  * Output Impedance = 48 Ohms

CTRL_CORE_CONTROL_DDRIO_0 = 0x00094a40
ddr1_d[7:0], ddr1_d[15:8]
  * Internal VREF disabled
ddr1_d[23:16], ddr1_d[31:24], ddr1_ecc_d[7:0]
  * Internal VREF disabled

CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT = 0x0001c1a7
  * Bit 16: EMIF1_EN_ECC = 1
EMIF_ECC_CTRL_REG = 0x00000000
  * Bit 31: reg_ecc_en = 0
  * Bit 30: reg_ecc_addr_rgn_prot = 0
  * Bit 29: reg_ecc_verify_dis = 0, enable ECC verification on reads (normal)
  * Bit 1: reg_ecc_addr_rgn_2_en = 0
  * Bit 0: reg_ecc_addr_rgn_1_en = 0
EMIF_ECC_ADDRESS_RANGE_1 = 0x00000000
EMIF_ECC_ADDRESS_RANGE_2 = 0x00000000
EMIF_1B_ECC_ERR_CNT = 0x00000000
EMIF_1B_ECC_ERR_THRSH = 0x00000000
EMIF_1B_ECC_ERR_DIST_1 = 0x00000000
EMIF_1B_ECC_ERR_DIST_1 = 0x00000000
EMIF_2B_ECC_ERR_ADDR_LOG = 0x00000000
EMIF_STATUS = 0x40000004

EMIF_SDRAM_CONFIG = 0x61822b32
EMIF_SDRAM_CONFIG_2 = 0x00000000
EMIF_SDRAM_REFRESH_CONTROL = 0x10001453
EMIF_SDRAM_TIMING_1 = 0xd113983c
EMIF_SDRAM_TIMING_2 = 0x31007fe3
EMIF_SDRAM_TIMING_3 = 0x40bf8f38
EMIF_READ_WRITE_LEVELING_RAMP_WINDOW = 0x00000000
EMIF_READ_WRITE_LEVELING_RAMP_CONTROL = 0x00000000
EMIF_READ_WRITE_LEVELING_CONTROL = 0x00000000
EMIF_DDR_PHY_CONTROL_1 = 0x0e24400e
  * Bits 4:0 READ_LATENCY = 14
  * Bit 9 PHY_FAST_DLL_LOCK = 0
  * Bits 17:10 PHY_DLL_LOCK_DIFF = 16
  * Bit 18 PHY_INVERT_CLKOUT = 1
  * Bit 19 PHY_DIS_CALIB_RST = 0
  * Bit 20 PHY_CLK_STALL_LEVEL = 0
  * Bit 21 PHY_HALF_DELAYS = 1
  * Bit 25 WRLVL_MASK = 1
  * Bit 26 RDLVLGATE_MASK = 1
  * Bit 27 RDLVL_MASK = 1

EMIF_EXT_PHY_CONTROL_1  = 0x04040100
EMIF_EXT_PHY_CONTROL_2  = 0x0000006a
EMIF_EXT_PHY_CONTROL_3  = 0x0000007d
EMIF_EXT_PHY_CONTROL_4  = 0x00000081
EMIF_EXT_PHY_CONTROL_5  = 0x0000007d
EMIF_EXT_PHY_CONTROL_6  = 0x00000089
EMIF_EXT_PHY_CONTROL_7  = 0x002f002f
EMIF_EXT_PHY_CONTROL_8  = 0x002f002f
EMIF_EXT_PHY_CONTROL_9  = 0x002f002f
EMIF_EXT_PHY_CONTROL_10 = 0x002f002f
EMIF_EXT_PHY_CONTROL_11 = 0x002f002f
EMIF_EXT_PHY_CONTROL_12 = 0x00830054
EMIF_EXT_PHY_CONTROL_13 = 0x00230061
EMIF_EXT_PHY_CONTROL_14 = 0x03120075
EMIF_EXT_PHY_CONTROL_15 = 0x03ad006e
EMIF_EXT_PHY_CONTROL_16 = 0x02de004d
EMIF_EXT_PHY_CONTROL_17 = 0x00630034
EMIF_EXT_PHY_CONTROL_18 = 0x00030041
EMIF_EXT_PHY_CONTROL_19 = 0x02f20055
EMIF_EXT_PHY_CONTROL_20 = 0x038d004e
EMIF_EXT_PHY_CONTROL_21 = 0x02be002d
EMIF_EXT_PHY_CONTROL_22 = 0x00800080
EMIF_EXT_PHY_CONTROL_23 = 0x00800080
EMIF_EXT_PHY_CONTROL_24 = 0x40010080
EMIF_EXT_PHY_CONTROL_25 = 0x08102040
EMIF_EXT_PHY_CONTROL_26 = 0x00000000
EMIF_EXT_PHY_CONTROL_27 = 0x00000000
EMIF_EXT_PHY_CONTROL_28 = 0x00000000
EMIF_EXT_PHY_CONTROL_29 = 0x00000000
EMIF_EXT_PHY_CONTROL_30 = 0x00000000
EMIF_EXT_PHY_CONTROL_31 = 0x00000000
EMIF_EXT_PHY_CONTROL_32 = 0x00000000
EMIF_EXT_PHY_CONTROL_33 = 0x00000000
EMIF_EXT_PHY_CONTROL_34 = 0x00000000
EMIF_EXT_PHY_CONTROL_35 = 0x00000000
EMIF_EXT_PHY_CONTROL_36 = 0x00000077

EMIF_EXT_PHY_STATUS_1  = 0x000d91f3
EMIF_EXT_PHY_STATUS_2  = 0xcb51b4d8
EMIF_EXT_PHY_STATUS_3  = 0x00000d86
EMIF_EXT_PHY_STATUS_4  = 0x000a3000
EMIF_EXT_PHY_STATUS_5  = 0x00099999
EMIF_EXT_PHY_STATUS_6  = 0x00004924
EMIF_EXT_PHY_STATUS_7  = 0x00000000
EMIF_EXT_PHY_STATUS_8  = 0x00000000
EMIF_EXT_PHY_STATUS_9  = 0x00000000
EMIF_EXT_PHY_STATUS_10 = 0x00000000
EMIF_EXT_PHY_STATUS_11 = 0x00000000
EMIF_EXT_PHY_STATUS_12 = 0x0700006a
EMIF_EXT_PHY_STATUS_13 = 0x0700007d
EMIF_EXT_PHY_STATUS_14 = 0x07000081
EMIF_EXT_PHY_STATUS_15 = 0x0700007d
EMIF_EXT_PHY_STATUS_16 = 0x07000089
EMIF_EXT_PHY_STATUS_17 = 0x00830054
EMIF_EXT_PHY_STATUS_18 = 0x00230061
EMIF_EXT_PHY_STATUS_19 = 0x00030041
EMIF_EXT_PHY_STATUS_20 = 0x03ad006e
EMIF_EXT_PHY_STATUS_21 = 0x02de004d
EMIF_EXT_PHY_STATUS_22 = 0x00630034
EMIF_EXT_PHY_STATUS_23 = 0x00030041
EMIF_EXT_PHY_STATUS_24 = 0x02f20055
EMIF_EXT_PHY_STATUS_25 = 0x038d004e
EMIF_EXT_PHY_STATUS_26 = 0x02be002d
EMIF_EXT_PHY_STATUS_27 = 0x11ff2122
EMIF_EXT_PHY_STATUS_28 = 0x0000001f

0 Brad Griffis over 4 years ago in reply to Pablo D'Angelo

TI__Guru*** 125430 points

This is along the lines of what I suspected, but zeroing out those registers is not a reliable solution. Can you compare the values of PHY_CTRL_22-35 from the spreadsheet with the values observed in your first DSS dump? Do they match? I'm trying to understand whether the issue was getting the spreadsheet values into the code, or if you have the wrong lengths in your spreadsheet.

0 Pablo D'Angelo over 4 years ago in reply to Brad Griffis

Prodigy 40 points

Hi Brad,
Values of PHY_CTRL_22-35 from spreadsheet are the same as DSS dump (without zeroing PHY_26 to 35). I've being testing Emif tool but any configuration modifies PHY_CTRL_22, 23, 24 or 25 spreadsheet's values.

PHY_CTRL_22-35 values are as follows:

0x00800080, // EMIF1_EXT_PHY_CTRL_22
0x00800080, // EMIF1_EXT_PHY_CTRL_23
0x40010080, // EMIF1_EXT_PHY_CTRL_24
0x08102040, // EMIF1_EXT_PHY_CTRL_25
0x005B00A0, // EMIF1_EXT_PHY_CTRL_26
0x005B00A0, // EMIF1_EXT_PHY_CTRL_27
0x005B00A5, // EMIF1_EXT_PHY_CTRL_28
0x005B00A6, // EMIF1_EXT_PHY_CTRL_29
0x005B00A9, // EMIF1_EXT_PHY_CTRL_30
0x00300043, // EMIF1_EXT_PHY_CTRL_31
0x00300043, // EMIF1_EXT_PHY_CTRL_32
0x0030004F, // EMIF1_EXT_PHY_CTRL_33
0x0030004F, // EMIF1_EXT_PHY_CTRL_34
0x0030005C, // EMIF1_EXT_PHY_CTRL_35

Best regards,
Pablo

0 Kevin S over 4 years ago in reply to Pablo D'Angelo

TI__Mastermind 26735 points

Hi Pablo,

I'd kindly request that you double check and compare your board layout file to the trace lengths in the XLS. The XLS file that was provided previously had the default values from that revision of the XLS, which most likely does not correspond to your system.

Best regards,
Kevin

0 Pablo D'Angelo over 4 years ago in reply to Kevin S

Prodigy 40 points

Hi Kevin,

We had very big values in 'step2-BoardDetails' so Emif tools generated default values on struct xxx_emif1_ext_phy_regs (on tab 'Register Values (U_Boot)'). That was re-checked, corrected and now it's working ok, except of Read Data Eye training that was masked.

Thanks Raul, Brad, Kevin.
Best regards,
Pablo

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