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AM5749: TIDL custom SSD isssue

Part Number: AM5749

Hi,

Our custom SSD model does not work.
1.In the host pc environment, the created SSD model can be recognized normally.
2.It succeeded in tidl_import, and it seems that the ssd_multibox execution result of example does not have any error.
DEFAULT_XXX of ssd_multibox/main.cpp is changed.

In the default one, the following log is output, but in the custom created one, the log is not output and it seems that it has completed with a timeout.
Even if the created multibox_0.png is displayed, the recognition BOX was not displayed.

Saving frame 0 to: frame_0.png
 0: (204, 57)-> (568, 300): horse, score = 0.525879
 1: (274, -4)-> (380, 173): person, score = 0.338013
Saving frame 0 with SSD multiboxes to: multibox_0.png
Loop total time (including read / write / opencv / print / etc): 601.4ms

I don't know how to debug.
Please give me advice on countermeasures.

The result of executing ssd_multibox is as follows.

cd /usr/share/ti/tidl/examples/ssd_multibox2
./ssd_multibox -i /home/root/cm_dl/cm_caffemodel/input_img/000000.jpg -v
[12878.281723] omap-iommu 58882000.mmu: 58882000.mmu: version 2.1
[12878.320418] omap-iommu 41501000.mmu: 41501000.mmu: version 3.0
[12878.326973] omap-iommu 41502000.mmu: 41502000.mmu: version 3.0
[12878.334406] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
[12878.340291] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
Input: /home/root/cm_dl/cm_lego_caffemodel/input_img/000000.jpg
-> Executor::Executor()
OCL Device: EVE created
Creating kernel ocl_tidl_setup
OCL Create B:0x55a4c
Arg[0]: 0x55a4c
OCL Create B:0x55adc
Arg[1]: 0x55adc
OCL Create B:0xbff14
Arg[2]: 0xbff14
OCL Create B:0xbffa4
Arg[3]: 0xbffa4
Kernel: EVE device 0 executing ocl_tidl_setup, context 0
Kernel: waiting context 0...
[eve 0] TIDL Device Trace: -> ocl_tidl_setup()
[eve 0] TIDL Device Trace: PARAM heap: Size 9437184, Free 6340248, Total requested 3096936
[eve 0] TIDL Device Trace: <- ocl_tidl_setup()
Kernel: finished execution
OCL Release B:0x55a4c
OCL Release B:0x55adc
OCL Release B:0xbff14
OCL Release B:0xbffa4
-> ExecutionObject::ExecutionObject()
Creating kernel ocl_tidl_cleanup
Creating kernel ocl_tidl_initialize
OCL Create B:0xbffa4
Arg[0]: 0xbffa4
OCL Create B:0xbff14
Arg[1]: 0xbff14
OCL Create B:0x55adc
Arg[2]: 0x55adc
OCL Create B:0x55a4c
Arg[3]: 0x55a4c
Arg[4]: local, 4
Creating kernel ocl_tidl_process
OCL Create B:0xc06e4
Arg[0]: 0xc06e4
OCL Create B:0xc079c
Arg[1]: 0xc079c
OCL Create B:(nil)
Arg[2]: (nil)
Arg[3]: 0xbed3e548
<- ExecutionObject::ExecutionObject()
Kernel: EVE device 0 executing ocl_tidl_initialize, context 0
Kernel: waiting context 0...
[eve 0] TIDL Device Trace: -> ocl_tidl_initialize()
[eve 0] TIDL Device Trace: -> SetupMemoryRecords()
[eve 0] TIDL Device Trace: <- SetupMemoryRecords()
[eve 0] TIDL Device Trace: -> InitializeInputOutputBuffers()
[eve 0] TIDL Device Trace: <- InitializeInputOutputBuffers()
[eve 0] TIDL Device Trace: <- ocl_tidl_initialize()
[eve 0] TIDL Device Trace: NETWORK heap: Size 67108864, Free 30793344, T otal requested 36315520
Kernel: finished execution
<- Executor::Executor()
-> Executor::Executor()
OCL Device: DSP created
Creating kernel ocl_tidl_setup
OCL Create B:0xc2a1c
Arg[0]: 0xc2a1c
OCL Create B:0xc2cb4
Arg[1]: 0xc2cb4
OCL Create B:0xc2f4c
Arg[2]: 0xc2f4c
OCL Create B:0xc31e4
Arg[3]: 0xc31e4
Kernel: DSP device 0 executing ocl_tidl_setup, context 0
Kernel: waiting context 0...
[core 0] TIDL Device Trace: -> ocl_tidl_setup()
[core 0] TIDL Device Trace: PARAM heap: Size 9437184, Free 6340248, Total requested 3096936
[core 0] TIDL Device Trace: <- ocl_tidl_setup()
Kernel: finished execution
OCL Release B:0xc2a1c
OCL Release B:0xc2cb4
OCL Release B:0xc2f4c
OCL Release B:0xc31e4
-> ExecutionObject::ExecutionObject()
Creating kernel ocl_tidl_cleanup
Creating kernel ocl_tidl_initialize
OCL Create B:0xc31e4
Arg[0]: 0xc31e4
OCL Create B:0xc2f4c
Arg[1]: 0xc2f4c
OCL Create B:0xc2cb4
Arg[2]: 0xc2cb4
OCL Create B:0xc2a1c
Arg[3]: 0xc2a1c
Arg[4]: local, 4
Creating kernel ocl_tidl_process
OCL Create B:0xc3c6c
Arg[0]: 0xc3c6c
OCL Create B:0xc3f64
Arg[1]: 0xc3f64
OCL Create B:(nil)
Arg[2]: (nil)
Arg[3]: 0xbed3e548
<- ExecutionObject::ExecutionObject()
Kernel: DSP device 0 executing ocl_tidl_initialize, context 0
Kernel: waiting context 0...
[core 0] TIDL Device Trace: -> ocl_tidl_initialize()
[core 0] TIDL Device Trace: -> SetupMemoryRecords()
[core 0] TIDL Device Trace: <- SetupMemoryRecords()
[core 0] TIDL Device Trace: -> InitializeInputOutputBuffers()
[core 0] TIDL Device Trace: <- InitializeInputOutputBuffers()
[core 0] TIDL Device Trace: <- ocl_tidl_initialize()
[core 0] TIDL Device Trace: NETWORK heap: Size 67108864, Free 66256000, T otal requested 852864
Kernel: finished execution
<- Executor::Executor()
Kernel: EVE device 0 executing ocl_tidl_process, context 0
[eve 0] TIDL Device Trace: -> ocl_tidl_process(frame 0, context 0)
[eve 0] TIDL Device Trace: <- ocl_tidl_process(frame 0, context 0)
-> [12905.564542] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
ExecutionObject::WaitAndReleaseContext(0)
Kernel: waiting cont[12905.576771] omap-iommu 40d02000.mmu: 40d02000.mmu : version 3.0
ext 0...
Kernel: finished execution
Kernel: DSP device 0 executing ocl_tidl_process, context 0
[core 0] TIDL Device Trace: -> ocl_tidl_process(frame 0, context 0)
[core 0] TIDL Device Trace: <- ocl_tidl_process(frame 0, context 0)
-> ExecutionObject::WaitAndReleaseContext(0)
Kernel: waiting context 0...
Ke[12905.612666] omap-iommu 41501000.mmu: 41501000.mmu: version 3.0
rnel: finished execution
Saving frame 0 with SSD multiboxes to:[12905.621229] omap-iommu 41502000.mmu: 41 502000.mmu: version 3.0
multibox_0.png
Loop total time (including read/write/opencv/print/etc): 2.421e+04ms
Kernel: EVE device 0 executing ocl_tidl_cleanup, context 0
Kernel: waiting context 0...
Kernel: finished execution
OCL Device: deleted
OCL Release B:0xc06e4
OCL Release B:0xc079c
OCL Release B:0xbffa4
OCL Release B:0xbff14
OCL Release B:0x55adc
OCL Release B:0x55a4c
Kernel: DSP device 0 executing ocl_tidl_cleanup, context 0
Kernel: waiting context 0...
Kernel: finished execution
OCL Device: deleted
OCL Release B:0xc3c6c
OCL Release B:0xc3f64
OCL Release B:0xc31e4
OCL Release B:0xc2f4c
OCL Release B:0xc2cb4
OCL Release B:0xc2a1c
ssd_multibox PASSED

Best Regards,
Shigehiro Tsuda



  • Hi,

    It was not recognized normally in the following environments as well as the custom model.
    model
    github.com/.../sparse

    github.com/.../sparse

    import
    \usr\share\ti\tidl\utils\test\testvecs\config\import\caffe\tidl_import_JDetNet_768x320.txt
    config
    \usr\share\ti\tidl\examples\test\testvecs\config\infer\tidl_config_jdetnet_voc.txt

    Are there any conditions?
    Could you provide an import file and a config file for ssd to work properly?

    How can I create * .y files in the following directories?
    If you have a * .y file viewer, please let me know.

    \usr\share\ti\tidl\examples\test\testvecs\input

    What is the difference between these files?
    preproc_0_768x320.y
    preproc_0_768x320_multi.y

    preproc_0_224x224.y
    preproc_2_224x224.y

    Best Regards,
    Shigehiro Tsuda

  • Hi,

    Is there update information?
    TIDL evaluation is not progressing with our customer.

    Best Regards,
    Shigehiro Tsuda

  • Hi Shigehiro-san,

    Apologies for the delay, several folks were out over the holiday week.

    We are taking a look and will get back to you this week.

    Regards,
    Mike

  • Tsuda-san, let me ask you few questions, to see if I understand the problem.

    1) Out-of-box demo SSD works OK, but custome SSD model import and runs OK, but there are not boxes displayed? Is my understanding correct?

    2) If so, did you get SSD model from github caffe-jacinto-models SSD? if not any other public place? In case I need it in order to reproduce the issue.

    3) *.y input image, should be the luminance component of an YUV image

    4) Which Linux PSDK and TIDL versions are you using? Linux PSDK 06_01_00_08?

    5) Which AM57x9 board are you using? (just to confirm number of EVE cores)

    6) When running the demo what is your configuration? want to check if running on DSP, EVE or both..

    From http://downloads.ti.com/mctools/esd/docs/tidl-api/example.html#ssd we have:

    The ssd network used in both categories has 43 layers. Input to the network is RGB image of size 768x320. Output is a list of boxes (up to 20), each box has information about the box coordinates, and which pre-trained category that the object inside the box belongs to. The example will take the network output, draw boxes accordingly, and create an output image. The network can be run entirely on either EVE or C66x. However, the best performance comes with running the first 30 layers as a group on EVE and the next 13 layers as another group on C66x. Our end-to-end example shows how easy it is to assign a Layer Group id to an Executor and how easy it is to construct an ExecutionObjectPipeline to connect the output of one Executor’s ExecutionObject to the input of another Executor’s ExecutionObject

    Thank you,

    Paula

  • Hi Mike,

    Thank you for your reply.

    I could understand that several staffs were on holiday last week.
    Please continue to follow me.

    Best Regards,
    Shigehiro Tsuda

  • Hi Paula,

    Thank you for the reply and your support.

    I answer your question below

    1) Out-of-box demo SSD works OK, but custome SSD model import and runs OK, but there are not boxes displayed? Is my understanding correct?

    [answer]
    Yes,it is correct with your understanding.

    2) If so, did you get SSD model from github caffe-jacinto-models SSD? if not any other public place? In case I need it in order to reproduce the issue.

    [answer]
    Yes,I get  SSD model from github caffe-jacinto-models SSD.

    3) *.y input image, should be the luminance component of an YUV image

    [answer]
    Thank you for your answer.
    Can you tell me how to create it?
    I use the raw image which created by this command.
    This is BGR image.

    convert sample.jpg resize 768x320 gravity center extent
    768x320 ./sample_rgb_768x320.png
    convert ./sample_rgb_768x320.png separate +channel swap 0,2 combine colorspace
    sRGB ./sample_bgr_768x320.png
    convert ./sample_bgr_768x320.png interlace plane BGR:sample_bgr_768x320.raw


    4) Which Linux PSDK and TIDL versions are you using? Linux PSDK 06_01_00_08?

    [answer]
    Yes,I use Linux PSDK 06_01_00_08

    5) Which AM57x9 board are you using? (just to confirm number of EVE cores)

    [answer]
    I use tmdsidkAM574 board.
    EVE core have two.

    6) When running the demo what is your configuration? want to check if running on DSP, EVE or both..

    [answer]
    I use both DSP and EVE.

    tidl import file and result file are the attached file.
    Is there problem?

    tidl_import_result2.txt
    # Default - 0
    randParams         = 0
    
    # 0: Caffe, 1: TensorFlow, Default - 0
    modelType          = 0
    
    # 0: Fixed quantization By tarininng Framework, 1: Dyanamic quantization by TIDL, Default - 1
    quantizationStyle  = 1
    
    # quantRoundAdd/100 will be added while rounding to integer, Default - 50
    quantRoundAdd      = 25
    
    numParamBits       = 8
    # 0 : 8bit Unsigned, 1 : 8bit Signed Default - 1
    inElementType      = 0
    
    inputNetFile      = "./deploy.prototxt"
    
    inputParamsFile    = "./cm-custom_ssdJacintoNetV2_iter_2000.caffemodel"
    
    outputNetFile      = "./tidl_net_cm-custom_ssdJacintoNetV2.bin"
    outputParamsFile   = "./tidl_param_cm-custom_ssdJacintoNetV2.bin"
    
    rawSampleInData = 1
    preProcType   = 4
    sampleInData = "./000000_bgr_768x320.raw"
    tidlStatsTool = "eve_test_dl_algo_ref.out"
    layersGroupId = 011111111111111111111111111111111111111111111120
    conv2dKernelType = 000000000000000011111111111111111111111111111111
    
    result
    
    =============================== TIDL import - parsing ===============================
    
    Caffe Network File : ./deploy.prototxt
    Caffe Model File   : ./cm-custom_ssdJacintoNetV2_iter_2000.caffemodel
    TIDL Network File  : ./tidl_net_cm-custom_ssdJacintoNetV2.bin
    TIDL Model File    : ./tidl_param_cm-custom_ssdJacintoNetV2.bin
    Name of the Network : ssdJacintoNetV2_deploy
    Num Inputs :               1
    
    Error in DetectionOutput layer: could not find parameters for detection_out!
     Num of Layer Detected :  57
      0, TIDL_DataLayer                , data                                      0,  -1 ,  1 ,   x ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  0 ,       0 ,       0 ,       0 ,       0 ,       1 ,       3 ,     320 ,     768 ,         0 ,
      1, TIDL_BatchNormLayer           , data/bias                                 1,   1 ,  1 ,   0 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  1 ,       1 ,       3 ,     320 ,     768 ,       1 ,       3 ,     320 ,     768 ,    737280 ,
      2, TIDL_ConvolutionLayer         , conv1a                                    1,   1 ,  1 ,   1 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  2 ,       1 ,       3 ,     320 ,     768 ,       1 ,      32 ,     160 ,     384 , 147456000 ,
      3, TIDL_ConvolutionLayer         , conv1b                                    1,   1 ,  1 ,   2 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  3 ,       1 ,      32 ,     160 ,     384 ,       1 ,      32 ,      80 ,     192 , 141557760 ,
      4, TIDL_ConvolutionLayer         , res2a_branch2a                            1,   1 ,  1 ,   3 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  4 ,       1 ,      32 ,      80 ,     192 ,       1 ,      64 ,      80 ,     192 , 283115520 ,
      5, TIDL_ConvolutionLayer         , res2a_branch2b                            1,   1 ,  1 ,   4 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  5 ,       1 ,      64 ,      80 ,     192 ,       1 ,      64 ,      40 ,      96 , 141557760 ,
      6, TIDL_ConvolutionLayer         , res3a_branch2a                            1,   1 ,  1 ,   5 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  6 ,       1 ,      64 ,      40 ,      96 ,       1 ,     128 ,      40 ,      96 , 283115520 ,
      7, TIDL_ConvolutionLayer         , res3a_branch2b                            1,   1 ,  1 ,   6 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  7 ,       1 ,     128 ,      40 ,      96 ,       1 ,     128 ,      40 ,      96 , 141557760 ,
      8, TIDL_PoolingLayer             , pool3                                     1,   1 ,  1 ,   7 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  8 ,       1 ,     128 ,      40 ,      96 ,       1 ,     128 ,      20 ,      48 ,    491520 ,
      9, TIDL_ConvolutionLayer         , res4a_branch2a                            1,   1 ,  1 ,   8 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  9 ,       1 ,     128 ,      20 ,      48 ,       1 ,     256 ,      20 ,      48 , 283115520 ,
     10, TIDL_ConvolutionLayer         , res4a_branch2b                            1,   1 ,  1 ,   9 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 10 ,       1 ,     256 ,      20 ,      48 ,       1 ,     256 ,      10 ,      24 , 141557760 ,
     11, TIDL_ConvolutionLayer         , res5a_branch2a                            1,   1 ,  1 ,  10 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 11 ,       1 ,     256 ,      10 ,      24 ,       1 ,     512 ,      10 ,      24 , 283115520 ,
     12, TIDL_ConvolutionLayer         , res5a_branch2b                            1,   1 ,  1 ,  11 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 12 ,       1 ,     512 ,      10 ,      24 ,       1 ,     512 ,      10 ,      24 , 141557760 ,
     13, TIDL_PoolingLayer             , pool6                                     1,   1 ,  1 ,  12 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 13 ,       1 ,     512 ,      10 ,      24 ,       1 ,     512 ,       5 ,      12 ,    122880 ,
     14, TIDL_PoolingLayer             , pool7                                     1,   1 ,  1 ,  13 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 14 ,       1 ,     512 ,       5 ,      12 ,       1 ,     512 ,       3 ,       6 ,     36864 ,
     15, TIDL_PoolingLayer             , pool8                                     1,   1 ,  1 ,  14 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 15 ,       1 ,     512 ,       3 ,       6 ,       1 ,     512 ,       2 ,       3 ,     12288 ,
     16, TIDL_PoolingLayer             , pool9                                     1,   1 ,  1 ,  15 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 16 ,       1 ,     512 ,       2 ,       3 ,       1 ,     512 ,       1 ,       2 ,      4096 ,
     17, TIDL_ConvolutionLayer         , ctx_output1                               1,   1 ,  1 ,   7 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 17 ,       1 ,     128 ,      40 ,      96 ,       1 ,     256 ,      40 ,      96 , 125829120 ,
     18, TIDL_ConvolutionLayer         , ctx_output2                               1,   1 ,  1 ,  12 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 18 ,       1 ,     512 ,      10 ,      24 ,       1 ,     256 ,      10 ,      24 ,  31457280 ,
     19, TIDL_ConvolutionLayer         , ctx_output3                               1,   1 ,  1 ,  13 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 19 ,       1 ,     512 ,       5 ,      12 ,       1 ,     256 ,       5 ,      12 ,   7864320 ,
     20, TIDL_ConvolutionLayer         , ctx_output4                               1,   1 ,  1 ,  14 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 20 ,       1 ,     512 ,       3 ,       6 ,       1 ,     256 ,       3 ,       6 ,   2359296 ,
     21, TIDL_ConvolutionLayer         , ctx_output5                               1,   1 ,  1 ,  15 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 21 ,       1 ,     512 ,       2 ,       3 ,       1 ,     256 ,       2 ,       3 ,    786432 ,
     22, TIDL_ConvolutionLayer         , ctx_output6                               1,   1 ,  1 ,  16 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 22 ,       1 ,     512 ,       1 ,       2 ,       1 ,     256 ,       1 ,       2 ,    262144 ,
     23, TIDL_ConvolutionLayer         , ctx_output1/relu_mbox_loc                 1,   1 ,  1 ,  17 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 23 ,       1 ,     256 ,      40 ,      96 ,       1 ,      16 ,      40 ,      96 ,  15728640 ,
     24, TIDL_FlattenLayer             , ctx_output1/relu_mbox_loc_perm            1,   1 ,  1 ,  23 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 24 ,       1 ,      16 ,      40 ,      96 ,       1 ,       1 ,       1 ,   61440 ,         1 ,
     25, TIDL_ConvolutionLayer         , ctx_output1/relu_mbox_conf                1,   1 ,  1 ,  17 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 25 ,       1 ,     256 ,      40 ,      96 ,       1 ,       8 ,      40 ,      96 ,   7864320 ,
     26, TIDL_FlattenLayer             , ctx_output1/relu_mbox_conf_perm           1,   1 ,  1 ,  25 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 26 ,       1 ,       8 ,      40 ,      96 ,       1 ,       1 ,       1 ,   30720 ,         1 ,
     28, TIDL_ConvolutionLayer         , ctx_output2/relu_mbox_loc                 1,   1 ,  1 ,  18 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 28 ,       1 ,     256 ,      10 ,      24 ,       1 ,      24 ,      10 ,      24 ,   1474560 ,
     29, TIDL_FlattenLayer             , ctx_output2/relu_mbox_loc_perm            1,   1 ,  1 ,  28 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 29 ,       1 ,      24 ,      10 ,      24 ,       1 ,       1 ,       1 ,    5760 ,         1 ,
     30, TIDL_ConvolutionLayer         , ctx_output2/relu_mbox_conf                1,   1 ,  1 ,  18 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 30 ,       1 ,     256 ,      10 ,      24 ,       1 ,      12 ,      10 ,      24 ,    737280 ,
     31, TIDL_FlattenLayer             , ctx_output2/relu_mbox_conf_perm           1,   1 ,  1 ,  30 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 31 ,       1 ,      12 ,      10 ,      24 ,       1 ,       1 ,       1 ,    2880 ,         1 ,
     33, TIDL_ConvolutionLayer         , ctx_output3/relu_mbox_loc                 1,   1 ,  1 ,  19 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 33 ,       1 ,     256 ,       5 ,      12 ,       1 ,      24 ,       5 ,      12 ,    368640 ,
     34, TIDL_FlattenLayer             , ctx_output3/relu_mbox_loc_perm            1,   1 ,  1 ,  33 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 34 ,       1 ,      24 ,       5 ,      12 ,       1 ,       1 ,       1 ,    1440 ,         1 ,
     35, TIDL_ConvolutionLayer         , ctx_output3/relu_mbox_conf                1,   1 ,  1 ,  19 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 35 ,       1 ,     256 ,       5 ,      12 ,       1 ,      12 ,       5 ,      12 ,    184320 ,
     36, TIDL_FlattenLayer             , ctx_output3/relu_mbox_conf_perm           1,   1 ,  1 ,  35 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 36 ,       1 ,      12 ,       5 ,      12 ,       1 ,       1 ,       1 ,     720 ,         1 ,
     38, TIDL_ConvolutionLayer         , ctx_output4/relu_mbox_loc                 1,   1 ,  1 ,  20 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 38 ,       1 ,     256 ,       3 ,       6 ,       1 ,      24 ,       3 ,       6 ,    110592 ,
     39, TIDL_FlattenLayer             , ctx_output4/relu_mbox_loc_perm            1,   1 ,  1 ,  38 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 39 ,       1 ,      24 ,       3 ,       6 ,       1 ,       1 ,       1 ,     432 ,         1 ,
     40, TIDL_ConvolutionLayer         , ctx_output4/relu_mbox_conf                1,   1 ,  1 ,  20 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 40 ,       1 ,     256 ,       3 ,       6 ,       1 ,      12 ,       3 ,       6 ,     55296 ,
     41, TIDL_FlattenLayer             , ctx_output4/relu_mbox_conf_perm           1,   1 ,  1 ,  40 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 41 ,       1 ,      12 ,       3 ,       6 ,       1 ,       1 ,       1 ,     216 ,         1 ,
     43, TIDL_ConvolutionLayer         , ctx_output5/relu_mbox_loc                 1,   1 ,  1 ,  21 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 43 ,       1 ,     256 ,       2 ,       3 ,       1 ,      16 ,       2 ,       3 ,     24576 ,
     44, TIDL_FlattenLayer             , ctx_output5/relu_mbox_loc_perm            1,   1 ,  1 ,  43 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 44 ,       1 ,      16 ,       2 ,       3 ,       1 ,       1 ,       1 ,      96 ,         1 ,
     45, TIDL_ConvolutionLayer         , ctx_output5/relu_mbox_conf                1,   1 ,  1 ,  21 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 45 ,       1 ,     256 ,       2 ,       3 ,       1 ,       8 ,       2 ,       3 ,     12288 ,
     46, TIDL_FlattenLayer             , ctx_output5/relu_mbox_conf_perm           1,   1 ,  1 ,  45 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 46 ,       1 ,       8 ,       2 ,       3 ,       1 ,       1 ,       1 ,      48 ,         1 ,
     48, TIDL_ConvolutionLayer         , ctx_output6/relu_mbox_loc                 1,   1 ,  1 ,  22 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 48 ,       1 ,     256 ,       1 ,       2 ,       1 ,      16 ,       1 ,       2 ,      8192 ,
     49, TIDL_FlattenLayer             , ctx_output6/relu_mbox_loc_perm            1,   1 ,  1 ,  48 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 49 ,       1 ,      16 ,       1 ,       2 ,       1 ,       1 ,       1 ,      32 ,         1 ,
     50, TIDL_ConvolutionLayer         , ctx_output6/relu_mbox_conf                1,   1 ,  1 ,  22 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 50 ,       1 ,     256 ,       1 ,       2 ,       1 ,       8 ,       1 ,       2 ,      4096 ,
     51, TIDL_FlattenLayer             , ctx_output6/relu_mbox_conf_perm           1,   1 ,  1 ,  50 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 51 ,       1 ,       8 ,       1 ,       2 ,       1 ,       1 ,       1 ,      16 ,         1 ,
     53, TIDL_ConcatLayer              , mbox_loc                                  1,   6 ,  1 ,  24 , 29 , 34 , 39 , 44 , 49 ,  x ,  x , 53 ,       1 ,       1 ,       1 ,   61440 ,       1 ,       1 ,       1 ,   69200 ,         1 ,
     54, TIDL_ConcatLayer              , mbox_conf                                 1,   6 ,  1 ,  26 , 31 , 36 , 41 , 46 , 51 ,  x ,  x , 54 ,       1 ,       1 ,       1 ,   30720 ,       1 ,       1 ,       1 ,   34600 ,         1 ,
     56, TIDL_DetectionOutputLayer     , detection_out                             1,   2 ,  1 ,  53 , 54 ,  x ,  x ,  x ,  x ,  x ,  x , 56 ,       1 ,       1 ,       1 ,   69200 ,       1 ,       1 ,       1 ,    5600 ,         1 ,
    Total Giga Macs : 2.1842
    
    =============================== TIDL import - calibration ===============================
    
    
    Processing config file ./tempDir/qunat_stats_config.txt !
    
    Running TIDL simulation for calibration.
    
      0, TIDL_DataLayer                ,  0,  -1 ,  1 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  0 ,    0 ,    0 ,    0 ,    0 ,    1 ,    3 ,  320 ,  768 ,
      1, TIDL_BatchNormLayer           ,  1,   1 ,  1 ,  0 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  1 ,    1 ,    3 ,  320 ,  768 ,    1 ,    3 ,  320 ,  768 ,
      2, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  1 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  2 ,    1 ,    3 ,  320 ,  768 ,    1 ,   32 ,  160 ,  384 ,
      3, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  2 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  3 ,    1 ,   32 ,  160 ,  384 ,    1 ,   32 ,   80 ,  192 ,
      4, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  3 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  4 ,    1 ,   32 ,   80 ,  192 ,    1 ,   64 ,   80 ,  192 ,
      5, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  4 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  5 ,    1 ,   64 ,   80 ,  192 ,    1 ,   64 ,   40 ,   96 ,
      6, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  5 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  6 ,    1 ,   64 ,   40 ,   96 ,    1 ,  128 ,   40 ,   96 ,
      7, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  6 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  7 ,    1 ,  128 ,   40 ,   96 ,    1 ,  128 ,   40 ,   96 ,
      8, TIDL_PoolingLayer             ,  1,   1 ,  1 ,  7 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  8 ,    1 ,  128 ,   40 ,   96 ,    1 ,  128 ,   20 ,   48 ,
      9, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  8 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  9 ,    1 ,  128 ,   20 ,   48 ,    1 ,  256 ,   20 ,   48 ,
     10, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  9 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 10 ,    1 ,  256 ,   20 ,   48 ,    1 ,  256 ,   10 ,   24 ,
     11, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 10 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 11 ,    1 ,  256 ,   10 ,   24 ,    1 ,  512 ,   10 ,   24 ,
     12, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 11 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 12 ,    1 ,  512 ,   10 ,   24 ,    1 ,  512 ,   10 ,   24 ,
     13, TIDL_PoolingLayer             ,  1,   1 ,  1 , 12 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 13 ,    1 ,  512 ,   10 ,   24 ,    1 ,  512 ,    5 ,   12 ,
     14, TIDL_PoolingLayer             ,  1,   1 ,  1 , 13 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 14 ,    1 ,  512 ,    5 ,   12 ,    1 ,  512 ,    3 ,    6 ,
     15, TIDL_PoolingLayer             ,  1,   1 ,  1 , 14 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 15 ,    1 ,  512 ,    3 ,    6 ,    1 ,  512 ,    2 ,    3 ,
     16, TIDL_PoolingLayer             ,  1,   1 ,  1 , 15 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 16 ,    1 ,  512 ,    2 ,    3 ,    1 ,  512 ,    1 ,    2 ,
     17, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  7 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 17 ,    1 ,  128 ,   40 ,   96 ,    1 ,  256 ,   40 ,   96 ,
     18, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 12 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 18 ,    1 ,  512 ,   10 ,   24 ,    1 ,  256 ,   10 ,   24 ,
     19, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 13 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 19 ,    1 ,  512 ,    5 ,   12 ,    1 ,  256 ,    5 ,   12 ,
     20, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 14 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 20 ,    1 ,  512 ,    3 ,    6 ,    1 ,  256 ,    3 ,    6 ,
     21, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 15 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 21 ,    1 ,  512 ,    2 ,    3 ,    1 ,  256 ,    2 ,    3 ,
     22, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 16 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 22 ,    1 ,  512 ,    1 ,    2 ,    1 ,  256 ,    1 ,    2 ,
     23, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 17 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 23 ,    1 ,  256 ,   40 ,   96 ,    1 ,   16 ,   40 ,   96 ,
     24, TIDL_FlattenLayer             ,  1,   1 ,  1 , 23 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 24 ,    1 ,   16 ,   40 ,   96 ,    1 ,    1 ,    1 ,61440 ,
     25, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 17 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 25 ,    1 ,  256 ,   40 ,   96 ,    1 ,    8 ,   40 ,   96 ,
     26, TIDL_FlattenLayer             ,  1,   1 ,  1 , 25 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 26 ,    1 ,    8 ,   40 ,   96 ,    1 ,    1 ,    1 ,30720 ,
     27, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 18 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 28 ,    1 ,  256 ,   10 ,   24 ,    1 ,   24 ,   10 ,   24 ,
     28, TIDL_FlattenLayer             ,  1,   1 ,  1 , 28 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 29 ,    1 ,   24 ,   10 ,   24 ,    1 ,    1 ,    1 , 5760 ,
     29, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 18 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 30 ,    1 ,  256 ,   10 ,   24 ,    1 ,   12 ,   10 ,   24 ,
     30, TIDL_FlattenLayer             ,  1,   1 ,  1 , 30 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 31 ,    1 ,   12 ,   10 ,   24 ,    1 ,    1 ,    1 , 2880 ,
     31, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 19 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 33 ,    1 ,  256 ,    5 ,   12 ,    1 ,   24 ,    5 ,   12 ,
     32, TIDL_FlattenLayer             ,  1,   1 ,  1 , 33 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 34 ,    1 ,   24 ,    5 ,   12 ,    1 ,    1 ,    1 , 1440 ,
     33, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 19 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 35 ,    1 ,  256 ,    5 ,   12 ,    1 ,   12 ,    5 ,   12 ,
     34, TIDL_FlattenLayer             ,  1,   1 ,  1 , 35 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 36 ,    1 ,   12 ,    5 ,   12 ,    1 ,    1 ,    1 ,  720 ,
     35, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 20 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 38 ,    1 ,  256 ,    3 ,    6 ,    1 ,   24 ,    3 ,    6 ,
     36, TIDL_FlattenLayer             ,  1,   1 ,  1 , 38 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 39 ,    1 ,   24 ,    3 ,    6 ,    1 ,    1 ,    1 ,  432 ,
     37, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 20 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 40 ,    1 ,  256 ,    3 ,    6 ,    1 ,   12 ,    3 ,    6 ,
     38, TIDL_FlattenLayer             ,  1,   1 ,  1 , 40 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 41 ,    1 ,   12 ,    3 ,    6 ,    1 ,    1 ,    1 ,  216 ,
     39, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 21 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 43 ,    1 ,  256 ,    2 ,    3 ,    1 ,   16 ,    2 ,    3 ,
     40, TIDL_FlattenLayer             ,  1,   1 ,  1 , 43 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 44 ,    1 ,   16 ,    2 ,    3 ,    1 ,    1 ,    1 ,   96 ,
     41, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 21 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 45 ,    1 ,  256 ,    2 ,    3 ,    1 ,    8 ,    2 ,    3 ,
     42, TIDL_FlattenLayer             ,  1,   1 ,  1 , 45 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 46 ,    1 ,    8 ,    2 ,    3 ,    1 ,    1 ,    1 ,   48 ,
     43, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 22 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 48 ,    1 ,  256 ,    1 ,    2 ,    1 ,   16 ,    1 ,    2 ,
     44, TIDL_FlattenLayer             ,  1,   1 ,  1 , 48 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 49 ,    1 ,   16 ,    1 ,    2 ,    1 ,    1 ,    1 ,   32 ,
     45, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 22 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 50 ,    1 ,  256 ,    1 ,    2 ,    1 ,    8 ,    1 ,    2 ,
     46, TIDL_FlattenLayer             ,  1,   1 ,  1 , 50 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 51 ,    1 ,    8 ,    1 ,    2 ,    1 ,    1 ,    1 ,   16 ,
     47, TIDL_ConcatLayer              ,  1,   6 ,  1 , 24 , 29 , 34 , 39 , 44 , 49 ,  x ,  x , 53 ,    1 ,    1 ,    1 ,61440 ,    1 ,    1 ,    1 ,69200 ,
     48, TIDL_ConcatLayer              ,  1,   6 ,  1 , 26 , 31 , 36 , 41 , 46 , 51 ,  x ,  x , 54 ,    1 ,    1 ,    1 ,30720 ,    1 ,    1 ,    1 ,34600 ,
     49, TIDL_DetectionOutputLayer     ,  1,   2 ,  1 , 53 , 54 ,  x ,  x ,  x ,  x ,  x ,  x , 56 ,    1 ,    1 ,    1 ,69200 ,    1 ,    1 ,    1 , 5600 ,
     50, TIDL_DataLayer                ,  0,   1 , -1 , 56 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  0 ,    1 ,    1 ,    1 , 5600 ,    0 ,    0 ,    0 ,    0 ,
    Layer ID    ,inBlkWidth  ,inBlkHeight ,inBlkPitch  ,outBlkWidth ,outBlkHeight,outBlkPitch ,numInChs    ,numOutChs   ,numProcInChs,numLclInChs ,numLclOutChs,numProcItrs ,numAccItrs  ,numHorBlock ,numVerBlock ,inBlkChPitch,outBlkChPitc,alignOrNot
          2           72           72           72           32           32           32            3           32            3            1            8            1            3           12            5         5184         1024            1
          3           40           34           40           32           32           32            8            8            8            4            8            1            2           12            5         1360         1024            1
          4           40           22           40           32           20           32           32           64           32            8            8            1            4            6            4          880          640            1
          5           40           22           40           32           20           32           16           16           16            8            8            1            2            6            4          880          640            1
          6           40           22           40           32           20           32           64          128           64            8            8            1            8            3            2          880          640            1
          7           40           22           40           32           20           32           32           32           32            8            8            1            4            3            2          880          640            1
          9           56           22           56           48           20           48          128          256          128            7            8            1           19            1            1         1232          960            1
         10           56           22           56           48           20           48           64           64           64            7            8            1           10            1            1         1232          960            1
         11           40           12           40           32           10           32          256          512          256            8            8            1           32            1            1          480          320            1
         12           40           12           40           32           10           32          128          128          128            8            8            1           16            1            1          480          320            1
         17           32           20           32           32           20           32          128          256          128            8            8            1           16            3            2          640          640            1
         18           32           10           32           32           10           32          512          256          512            8            8            1           64            1            1          320          320            1
         19           16            5           16           16            5           16          512          256          512            8            8            1           64            1            1           80           80            1
         20           16            3           16           16            3           16          512          256          512            8            8            1           64            1            1           48           48            1
         21           16            2           16           16            2           16          512          256          512            8            8            1           64            1            1           32           32            1
         22           16            1           16           16            1           16          512          256          512            8            8            1           64            1            1           16           16            1
         23           32           20           32           32           20           32          256           16          256            8            8            1           32            3            2          640          640            1
         25           32           20           32           32           20           32          256            8          256            8            8            1           32            3            2          640          640            1
         27           32           10           32           32           10           32          256           24          256            8            8            1           32            1            1          320          320            1
         29           32           10           32           32           10           32          256           16          256            8            8            1           32            1            1          320          320            1
         31           16            5           16           16            5           16          256           24          256            8            8            1           32            1            1           80           80            1
         33           16            5           16           16            5           16          256           16          256            8            8            1           32            1            1           80           80            1
         35           16            3           16           16            3           16          256           24          256            8            8            1           32            1            1           48           48            1
         37           16            3           16           16            3           16          256           16          256            8            8            1           32            1            1           48           48            1
         39           16            2           16           16            2           16          256           16          256            8            8            1           32            1            1           32           32            1
         41           16            2           16           16            2           16          256            8          256            8            8            1           32            1            1           32           32            1
         43           16            1           16           16            1           16          256           16          256            8            8            1           32            1            1           16           16            1
         45           16            1           16           16            1           16          256            8          256            8            8            1           32            1            1           16           16            1
    
    Processing Frame Number : 0
    
     Layer    1 : Out Q :      254 , TIDL_BatchNormLayer  , PASSED  #MMACs =     0.74,     0.74, Sparsity :   0.00
     Layer    2 : Out Q :     6267 , TIDL_ConvolutionLayer, PASSED  #MMACs =   147.46,   111.82, Sparsity :  24.17
     Layer    3 : Out Q :     6824 , TIDL_ConvolutionLayer, PASSED  #MMACs =   141.56,    78.40, Sparsity :  44.62
     Layer    4 : Out Q :    11198 , TIDL_ConvolutionLayer, PASSED  #MMACs =   283.12,   147.46, Sparsity :  47.92
     Layer    5 : Out Q :    13528 , TIDL_ConvolutionLayer, PASSED  #MMACs =   141.56,    74.53, Sparsity :  47.35
     Layer    6 : Out Q :    18712 , TIDL_ConvolutionLayer, PASSED  #MMACs =   283.12,   147.36, Sparsity :  47.95
     Layer    7 : Out Q :    15612 , TIDL_ConvolutionLayer, PASSED  #MMACs =   141.56,    73.88, Sparsity :  47.81
     Layer    8 :TIDL_PoolingLayer,     PASSED  #MMACs =     0.12,     0.12, Sparsity :   0.00
     Layer    9 : Out Q :    16635 , TIDL_ConvolutionLayer, PASSED  #MMACs =   283.12,   148.61, Sparsity :  47.51
     Layer   10 : Out Q :    16681 , TIDL_ConvolutionLayer, PASSED  #MMACs =   141.56,    74.50, Sparsity :  47.37
     Layer   11 : Out Q :    31142 , TIDL_ConvolutionLayer, PASSED  #MMACs =   283.12,   147.26, Sparsity :  47.99
     Layer   12 : Out Q :     1563 , TIDL_ConvolutionLayer, PASSED  #MMACs =   141.56,    57.05, Sparsity :  59.70
     Layer   13 :TIDL_PoolingLayer,     PASSED  #MMACs =     0.03,     0.03, Sparsity :   0.00
     Layer   14 :TIDL_PoolingLayer,     PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00
     Layer   15 :TIDL_PoolingLayer,     PASSED  #MMACs =     0.00,     0.00, Sparsity :   0.00
     Layer   16 :TIDL_PoolingLayer,     PASSED  #MMACs =     0.00,     0.00, Sparsity :   0.00
     Layer   17 : Out Q :    10483 , TIDL_ConvolutionLayer, PASSED  #MMACs =   125.83,   125.83, Sparsity :   0.00
     Layer   18 : Out Q :     6560 , TIDL_ConvolutionLayer, PASSED  #MMACs =    31.46,    31.40, Sparsity :   0.19
     Layer   19 : Out Q :    10169 , TIDL_ConvolutionLayer, PASSED  #MMACs =     7.86,     7.81, Sparsity :   0.72
     Layer   20 : Out Q :    12413 , TIDL_ConvolutionLayer, PASSED  #MMACs =     2.36,     2.25, Sparsity :   4.51
     Layer   21 : Out Q :    13955 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.79,     0.74, Sparsity :   6.22
     Layer   22 : Out Q :    18080 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.26,     0.25, Sparsity :   6.06
     Layer   23 : Out Q :     3515 , TIDL_ConvolutionLayer, PASSED  #MMACs =    15.73,    15.70, Sparsity :   0.20
     Layer   24 :TIDL_FlattenLayer, PASSED  #MMACs =     0.06,     0.06, Sparsity :   0.00
     Layer   25 : Out Q :     2235 , TIDL_ConvolutionLayer, PASSED  #MMACs =     7.86,     7.86, Sparsity :   0.00
     Layer   26 :TIDL_FlattenLayer, PASSED  #MMACs =     0.03,     0.03, Sparsity :   0.00
     Layer   27 : Out Q :     8044 , TIDL_ConvolutionLayer, PASSED  #MMACs =     1.47,     1.47, Sparsity :   0.13
     Layer   28 :TIDL_FlattenLayer, PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.00
     Layer   29 : Out Q :     2251 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.98,     0.98, Sparsity :   0.10
     Layer   30 :TIDL_FlattenLayer, PASSED  #MMACs =     0.00,     0.00, Sparsity :   0.00
     Layer   31 : Out Q :     7807 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.37,     0.37, Sparsity :   0.33
     Layer   32 :TIDL_FlattenLayer, PASSED  #MMACs =     0.00,     0.00, Sparsity :   0.00
     Layer   33 : Out Q :     3413 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.25,     0.25, Sparsity :   0.20
     Layer   34 :TIDL_FlattenLayer, PASSED  #MMACs =     0.00,     0.00, Sparsity :   0.00
     Layer   35 : Out Q :     9928 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.11,     0.11, Sparsity :   1.95
     Layer   36 :TIDL_FlattenLayer, PASSED  #MMACs =     0.00,     0.00, Sparsity :   0.00
     Layer   37 : Out Q :     4070 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.07,     0.07, Sparsity :   0.59
     Layer   38 :TIDL_FlattenLayer, PASSED  #MMACs =     0.00,     0.00, Sparsity :   0.00
     Layer   39 : Out Q :     9309 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.02,     0.02, Sparsity :   1.37
     Layer   40 :TIDL_FlattenLayer, PASSED  #MMACs =     0.00,     0.00, Sparsity :   0.00
     Layer   41 : Out Q :     4367 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.01,     0.01, Sparsity :   0.59
     Layer   42 :TIDL_FlattenLayer, PASSED  #MMACs =     0.00,     0.00, Sparsity :   0.00
     Layer   43 : Out Q :    15272 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.01,     0.01, Sparsity :   1.46
     Layer   44 :TIDL_FlattenLayer, PASSED  #MMACs =     0.00,     0.00, Sparsity :   0.00
     Layer   45 : Out Q :     6094 , TIDL_ConvolutionLayer, PASSED  #MMACs =     0.00,     0.00, Sparsity :   0.59
     Layer   46 :TIDL_FlattenLayer, PASSED  #MMACs =     0.00,     0.00, Sparsity :   0.00
     Layer   47 : Out Q :     3529 , TIDL_ConcatLayer, PASSED  #MMACs =     0.00,     0.00, Sparsity :    nan
     Layer   48 : Out Q :     2244 , TIDL_ConcatLayer, PASSED  #MMACs =     0.00,     0.00, Sparsity :    nan
     Layer   49 :
    Target: number label value xmin  ymin  xmax  ymax
    Target:  0.00  1.00  0.90  0.03  0.54  0.06  0.64
    Target:  1.00  1.00  0.66  0.71  0.17  0.53  0.81
    Target:  2.00  1.00  0.66  1.04  0.49  0.93  0.52
    Target:  3.00  1.00  0.56  0.50  0.93  0.53  1.04
    Target:  4.00  1.00  0.47  0.50  0.57  0.53  0.65
    Target:  5.00  1.00  0.36  0.54  0.02  0.56  0.06
    Target:  6.00  1.00  0.36  0.53  0.04  0.50  0.50
    Target:  7.00  1.00  0.29  0.53  0.30  0.55  0.37
    Target:  8.00  1.00  0.24 -0.01  0.75  0.03  0.60
    Target:  9.00  1.00  0.10  0.44  0.36  0.49  0.49
    Target: 10.00  1.00  0.06  0.25  0.91  0.28  1.02
    Target: 11.00  1.00  0.04  1.02  0.24  0.91  0.27
    Target: 12.00  1.00  0.02  0.20  0.46  0.91 -0.05
    Target: 13.00  1.00  0.02  0.49  0.17  0.53  0.21
    Target: 14.00  1.00  0.02  0.28  0.90  0.35  1.02
    Target: 15.00  1.00  0.02  0.50  1.04  0.48  0.93
    Target: 16.00  1.00  0.01  0.12  0.50  0.37  1.11
    Target: 17.00  1.00  0.01  0.46  0.11  0.55  0.21
    Target: 18.00  1.00  0.01  0.00  0.32  0.35  1.26
    Target: 19.00  1.00  0.01  0.48  0.56  0.51  0.64
    Target: 20.00  1.00  0.01  0.51  0.17  0.54  0.21
    Target: 21.00  1.00  0.01  0.41  0.97  0.45  1.01
    Target: 22.00  1.00  0.01  0.33  0.23  0.37  0.29
    Target: 23.00  1.00  0.01  0.69  0.93  0.76  1.03
    Target: 24.00  1.00  0.01  0.57 -0.22  0.67  0.39
    Target: 25.00  1.00  0.01  0.54  0.29  0.57  0.36
    Target: 26.00  1.00  0.01  0.60  0.61  0.67  0.73
    Target: 27.00  1.00  0.01  0.38  0.85  0.47  0.50
     #MMACs =     0.01,     0.01, Sparsity :   0.00
    End of config list found !


    Best Regards,
    Shigehiro Tsuda

  • Tsuda-san, I was able to import  SSD 512x512 (voc0712_ssdJacintoNetV2_iter_104000.caffemodel) from https://github.com/tidsp/caffe-jacinto-models and run it with camera as input. Let me share some configuration files and steps with you, in case it helps.

    1) TIDL import config file for JDetNet: 

    tidl_import_jdetNet_modif.txt
    # Default - 0
    randParams         = 0 
    
    # 0: Caffe, 1: TensorFlow, Default - 0
    modelType          = 0 
    
    # 0: Fixed quantization By tarininng Framework, 1: Dyanamic quantization by TIDL, Default - 1
    quantizationStyle  = 1 
    
    # quantRoundAdd/100 will be added while rounding to integer, Default - 50
    quantRoundAdd      = 25
    
    numParamBits       = 8
    # 0 : 8bit Unsigned, 1 : 8bit Signed Default - 1
    inElementType      = 0 
    
    inputNetFile      = "/home/root/TIDL_utils_bin/OD_SSD_JDetNet/ssd512x512_ds_PSP_dsFac_32_fc_0_hdDS8_1_kerMbox_3_1stHdSameOpCh_1/sparse/deploy.prototxt"
    
    inputParamsFile    = "/home/root/TIDL_utils_bin/OD_SSD_JDetNet/ssd512x512_ds_PSP_dsFac_32_fc_0_hdDS8_1_kerMbox_3_1stHdSameOpCh_1/sparse/voc0712_ssdJacintoNetV2_iter_104000.caffemodel"
    
    outputNetFile      = "/home/root/TIDL_utils_bin/tidl_net_jdetNet_512x512.bin"
    outputParamsFile   = "/home/root/TIDL_utils_bin/tidl_param_jdetNet_512x512.bin"
    
    rawSampleInData = 1
    preProcType   = 4
    sampleInData = "/home/root/TIDL_utils_bin/testvecs/input/trace_dump_0_768x320.y"
    tidlStatsTool = "eve_test_dl_algo_ref.out"
    layersGroupId = 0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	2	0
    conv2dKernelType = 0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
    
    
     

    I believe this is similar to what you are using.. as your results (attached in above post) looks similar to mine.

    2) Then I copied output "tidl_param_jdetNet_512x512.bin" and "tidl_net_jdetNet_512x512.bin" inside /usr/share/ti/tidl/examples/test/testvecs/config/tidl_models/ folder

    3) Next, I modified /usr/share/ti/tidl/examples/test/testvecs/config/infer/tidl_config_jdetnet.txt to reflect new Width/Height dimensions.. I keep it inData as  "preproc_0_768x320.y" but you can find a better *512x512.y or cropped it..

    1882.tidl_config_jdetnet.txt
    numFrames     = 1
    preProcType   = 4
    netBinFile    = "../test/testvecs/config/tidl_models/tidl_net_jdetNet_512x512.bin"
    paramsBinFile = "../test/testvecs/config/tidl_models/tidl_param_jdetNet_512x512.bin"
    inWidth       = 512
    inHeight      = 512
    inNumChannels = 3
    inData        = "../test/testvecs/input/preproc_0_768x320.y"
    outData       = "./stats_tool_out.bin"
    

    4) For running the demo I used below commands:

    root@am57xx-evm:/usr/share/ti/tidl/examples/ssd_multibox# /etc/init.d/matrix-gui-2.0 stop
    root@am57xx-evm:/usr/share/ti/tidl/examples/ssd_multibox# ./ssd_multibox -i camera -f 500

    I noticed some latency but in general boxes shows OK, at least it detects me, and detected a toy car I had handy.

    Thank you,

    Paula

  • Hi Paula,

    Thank you for your support.
    I will try like your answer.

    There are two questions.
    1.
    The default model of ssd_multibox sample is jdetnet_voc.
    I think you should modify tidl_config_jdetnet_voc.
    Is it wrong?

    2.
    What should be defined "network" of jdetnet_voc_objects.json?
    The default is "jdetnet_voc".
    Result of tidl import is the following network name.

    caffe Network File : ./deploy.prototxt
    Caffe Model File : ./cm-custom_ssdJacintoNetV2_iter_1000.caffemodel
    TIDL Network File : ./tidl_net_cm-custom_ssdJacintoNetV2.bin
    TIDL Model File : ./tidl_param_cm-custom_ssdJacintoNetV2.bin
    Name of the Network : ssdJacintoNetV2_deploy

    Does it need to change?

    Best Regards,
    Shigehiro Tsuda

  • Tsuda-san, my bad, if I only use "./ssd_multibox -i camera -f 500" in command line for executing ssd_multibox application, then by default "jdetnet_voc" was used. Then, I was evaluating the wrong NN model binary.

    After trying the run the new NN model binary "tidl_param_jdetNet_512x512.bin" and "tidl_net_jdetNet_512x512.bin" it actually didn't work.

    In order to understand what it could be the issue, I used "tidl_viewer" and noticed the division of layers between group 0/1 and group 2 were wrong. I knew it was wrong after creating a similar *.svg graph for OOB "tidl_net_jdetNet_ssd.bin" and comparing them.

    So, I proceed to modify my "tidl_import_jdetNet_modif.txt" "layersGroupId". I didn't used "conv2dKernelType", but you can give a try to this.

    Also, using ffmpeg in Ubuntu, I scaled and crop 1920x1080 *.mp4 video to a 512x512 *.mp4 (attached).

    With above changes, now new 512x512 SSD runs OK. I used: ./ssd_multibox -c jdetnet -l jdetnet_objects.json clips/pexels_2_512x512.mp4

    Answering your questions:

    Q1) yes you need to modify tidl_config_jdetnet_voc if using default..

    Q2) you just need to be careful to call the correct network according with the class list of objects you want to use in *.json

    I am attaching my NN model binaries, just in case they help. 

    0131.tidl_import_jdetNet_modif.txt
    # Default - 0
    randParams         = 0 
    
    # 0: Caffe, 1: TensorFlow, Default - 0
    modelType          = 0 
    
    # 0: Fixed quantization By tarininng Framework, 1: Dyanamic quantization by TIDL, Default - 1
    quantizationStyle  = 1 
    
    # quantRoundAdd/100 will be added while rounding to integer, Default - 50
    quantRoundAdd      = 25
    
    numParamBits       = 8
    # 0 : 8bit Unsigned, 1 : 8bit Signed Default - 1
    inElementType      = 0 
    
    inputNetFile      = "/home/root/TIDL_utils_bin/OD_SSD_JDetNet/ssd512x512_ds_PSP_dsFac_32_fc_0_hdDS8_1_kerMbox_3_1stHdSameOpCh_1/sparse/deploy.prototxt"
    
    inputParamsFile    = "/home/root/TIDL_utils_bin/OD_SSD_JDetNet/ssd512x512_ds_PSP_dsFac_32_fc_0_hdDS8_1_kerMbox_3_1stHdSameOpCh_1/sparse/voc0712_ssdJacintoNetV2_iter_104000.caffemodel"
    
    outputNetFile      = "/home/root/TIDL_utils_bin/tidl_net_jdetNet_512x512.bin"
    outputParamsFile   = "/home/root/TIDL_utils_bin/tidl_param_jdetNet_512x512.bin"
    
    rawSampleInData = 1
    preProcType   = 4
    sampleInData = "/home/root/TIDL_utils_bin/testvecs/input/pexels_2_515x512_frame.y"
    tidlStatsTool = "eve_test_dl_algo_ref.out"
    layersGroupId = 0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	2	1	2	1	2	1	2	1	2	1	2	1	2	1	2	1	2	1	2	1	2	1	2	2	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
    
    

    tidl_net_jdetNet_512x512.bin

    tidl_param_jdetNet_512x512.bin

  • Hi Paula,

    Thank you for quick reply and your support.
    I would like to try your answer procedure.

    Your import file is the following parameter setting of sampleInData.
    sampleInData = "/home/root/TIDL_utils_bin/testvecs/input/pexels_2_515x512_frame.y"

    Please tell me how to create "pexels_2_515x512_frame.y"

    Best Regards,
    Shigehiro Tsuda

  • Tsuda-san, just to clarify *.y frames are actually RGB planar (NCHW - plane interleaved) and not the luminance component from a YUV as I previously suspected.

    thank you,

    Paula

  • Hi Paula,

    Thank you for your support.

    I could work normaly with customer model by the "layersGroupId" change which you were answered. 

    It seems that tidl import is the cause.
    There was no error in particular, was there any limitation?
    Since it seems that the same thing happens if we execute tidl import with other models,
    I would like to confirm.

    Best Regards,
    Shigehiro Tsuda

  • Hi Tsuda-san, I see your point.. but, I believe, it is more a performance limitation than a layer coverage limitation, I will double check though. So, if I am correct, no sure if this intelligence could be in-build in TIDL import tool.. but in anyhow, you are right it would be great to have it.

    So, just to summarize (for a broader audience), the issue was that some consecutive layers at the end were alternatively  assigned to Layergroup1 followed by layers in  layergroup2, followed by layers in Layergroup1, and so and so.. This back and forth reduced performance and creates data bottlenecks..

    For your reference, from PSDK TIDL user guide we have:

    "In order to use both DSP and EVE accelerators, it is possible to split the network into two sub-graphs using concept of layergroups. Than one layer group can be executed on EVE and another on DSP. Output of first group (running on EVE) will be used as input for DSP. Input and output layer belong to layer group 0. Layergroup 1 is dispatched to EVE, and layergroup 2 to DSP."

    Thank you,

    Paula

  • Hi Paula,

    Thank you for your support.
    Sorry for the delay to reply you.

    I understood that it was more a performance limitation than a layer coverage limitation.
    I hope that TIDL import tool will be able to solve their limitations.

    Best Regards,
    Shigehiro Tsuda