Hi,

Yes, you must use the SmartReflex pins of the device in your hardware design. This is NOT optional.
LM10011 is one option to realize the SmartReflex circuitry, as you can see in Section 2.2.1 CVDD in the Hardware Design Guide for Keystone devices. You can also use UCD92xx.

Best Regards,
Yordan

Hi Wang,

Not sure I understand what you mean by:
 

I did not use the DDR3 SDRAM ,but the current of VDD1V5 Jump among 0.1A 、0.15A

can I power down the AVDDA2, VREFSSTL ,VDD1V5, and  left DDRCLKP/N  floating

Refer to Section 6.8.4 Unused DDR3 Pin Requirement from the Hardware design guide: https://www.ti.com/lit/an/sprabi2d/sprabi2d.pdf

You should also have in mind Section 3.6 Unused Clock Inputs from the same document. As for the ddr clock you should must have in mind the following recommendations by Tom:
  https://e2e.ti.com/support/processors/f/791/t/830921

Best Regards,
Yordan