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Part Number: AM5728
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In reply to Biser Gatchev-XID:
In reply to user6236094:
I have not seen this reported previously. Which board did you observe this on?
In reply to -DK-:
I've tried to reproduce this issue in the lab using our AM572x IDK EVM, but I am unable to see the issue. My suspicion is that your board has a sequencing issue that is not present on our EVM. I am not a power expert, so I'll need to pull in a coworker for this. Please allow a day or so for them to respond.
Have you verified that the power sequencing for all rails is correct as per the diagram above? This glitch may be a result of a sequencing issue.
HI,Thank you for your answer.I will answer below.
>Have you verified that the power sequencing for all rails is correct as per the diagram above?
Yes. We have confirmed that the power-up sequence is correct. And the power supply of the SITARA processor uses a dedicated power management Unit(TPS659037)
However, the input timing of "xi_OSC" was the clock input after "vdda_osc" was supplied. It looks like the following figure.
Will the following contents affect this problem?
Good news, I was finally able to reproduce this in our lab. Initially I was unable to see the issue because I had a USB device attached and even this tiny load was sufficient to squelch the signal. Once I removed the USB device, the 2.5V glitch was visible.
After conferring with my Design Engineer counterpart, we are in agreement that this voltage on D+ is the result of an internal leakage path that is present prior to chip reset. I measured this leakage at ~200uA which is well within the specified limits for this interface and I/O cell (3.3V Analog) design so no resulting issues are expected.
HI,Thank you for your answer.Please tell me the following points.
>I measured this leakage at ~200uA which is well within the specified limits for this interface >and I/O cell (3.3V Analog) design so no resulting issues are expected.
Regarding the above answer, I couldn't understand why this glitch is not a problem.
If a glitch occurs when SITARA power is turned on, if the connected device does not have the resistance to the non-energized state (when VBUS = “OFF”), the connected device may be destroyed.
Also,Does this glitch have no problem on the SITARA side, but does it mean that there may be a problem with devices connected to USB 2.0?
Can you tell me in detail why there is no problem?
Given the sheer number of USB devices in the market, I don't think that anyone can guarantee that this artifact will not present a problem for any of them. However, from a practical standpoint I do not expect this to present a problem for a connected device either given that these pins are 3.3V analog I/O on both sides of the connection and that the voltage potential presented while the SoC is in reset is well within the operational parameters for the interface.
I did review the USB specification looking for guidance on this topic and did not find it addressed.
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