• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 2 answers
  • Subscribers 104 subscribers
  • Views 250 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5716: VPDMA descriptor

Masashi Ohhashi
Expert 4805 points
Part Number: AM5716

Hi,

my customer has some questions about descriptor in VIP on AM5716.　They want to check if the Descriptor is loaded or completed.

1. Should we use the Outbound Data Transfer Descriptor to transfer data from VPDMA to DDR3?

2. Is the bit[23:16] LISTx_BUSY bit (Read Only) in VIP_LIST_STAT_SYNC register (0x4897 D00C) correct for checking the Descriptor status? And, does each bit mean 1 = Descriptor is loaded, 0 = Descriptor is completed?

3. There is the bit[9] RDY bit in VIP_LIST_ATTR register (0x4897 D008).  Does the bit mean 1 = Descriptor is loaded, 0 = Descriptor is completed?

Best Regards,

M.Ohhashi

  • 0
    TI__Mastermind 28788 points

    Hi,

    Are you asking about the Processor-SDK-RTOS VPS drivers? Are you writing your own driver?

    Documentation on the drivers can be located here: http://software-dl.ti.com/processor-sdk-rtos/esd/docs/06_01_00_08/rtos/index_device_drv.html#vps-drivers

    More detailed documentation can be located in <PDK>\packages\ti\drv\vps\docs\doxygen\html\index.html.

    Details on the VPS hardware operation can be located in the AM571x TRM, which is available here: http://www.ti.com/product/AM5716/technicaldocuments

    Regards,
    Frank

  • 0 in reply to Frank Livingston
    TI__Expert 4805 points

    Hi Frank-san,

    Thank you for your reply.

    we read the TRM and other documents. But the description is not clear for us. So we would like to confirm them.

    We would appreciate it if you would explain them.

    Best Regards,

    M.Ohhashi

  • 0 in reply to Masashi Ohhashi
    TI__Guru 68780 points

    Ohhashi,

    the LISTx_BUSY bit fields are an indication that the descriptor is currently being processed/active (LISTx_BUSY=1) or has completed/idle (LISTx_BUSY=0).  I'm not sure what you mean by "loaded"

    The RDY signal is an indication that the list cannot be written because either the firmware is being loaded, or the list you are trying to write to is still active.   You must wait for this bit to be high to start the processing of a new list of descriptors.

    Regards,

    James  

  • 0 in reply to JJD
    TI__Expert 4805 points

    James-san,

    Thank you for your answer. It is helpful for us.

    my customer have more question.

    Currently, even when the Descriptor is loaded, VIP_LIST_ATTR [19] RDY bit is not set and loading is not completed, so VPDMA does not work. 

    There is described "FIRMWARE" of "List Manager needs to be loaded with FIRMWARE" in "9.4.8.2.3.List". Does “FIRMWARE” indicate the operation to write the buffer address of the Descriptor to the VIP_LIST_ADDR register first after VPDMA reset? Or is there a FIRMWARE in the SDK that loads the List Manager?

    VIP setting is confirmed by SDK sample program "vps_loopbackExample_idkAM572x_armExampleProject".In the code, there was a place where "#define VPSHAL_VPDMAFIRMWARE_288" or "#define VPSHAL_VPDMAFIRMWARE_1B8" was set to DDR3 and the address was written to the VPDMA_LIST_ADDR register. Perhaps 9.4.8.2.3 List “List Manager needs to be loaded with FIRMWARE” “FIRMWARE” points to the table defined in #define above, and will the List Manager be loaded with that table?

    Best Regards,

    M.Ohhashi

  • 0 in reply to Masashi Ohhashi
    TI__Mastermind 28788 points

    Hi,

    We don't support customer driver development. If you have questions concerning PRSDK software, then we can attempt to answer these. Hardware and TRM questions should be directed to a hardware applications team. I'll see if I can redirect this thread.

    Thanks for your patience.

    Regards,
    Frank

  • 0 in reply to Frank Livingston
    TI__Expert 4805 points

    Hi,

    I would appreciate it if you would send redirect applications team.

    They have more questions.

    VIP setting is confirmed by SDK sample program "vps_loopbackExample_idkAM572x_armExampleProject"

    Even if the #define VPSHAL_VPDMAFIRMWARE_288 is set to DDR3 and the address is written to the VPDMA_LIST_ADDR register on the designed PT board (AM5716), the VIP_LIST_ATTR [19] RDY bit is not set to 1. VIP_LIST_ATTR [19] The RDY bit was not set to 1. “#Define VPSHAL_VPDMAFIRMWARE_1B8” gave similar results.

    <procedure>

    1.Set the #define table to DDR3 (0x8001 1FC0)

    2.Write `` 0x0001 0001 '' to the VIP_CLKC_CLKEN register (0x4897 0100)

    3.Write `` 0x0000 0001 '' to the VIP_CLKC_RST register (0x4897 0104)

    4.Write `` 0x0000 0000 '' to the VIP_CLKC_RST register (0x4897 0104)

    5.Write the address (0x8001 1FC0) where the #define table is set to the VIP_LIST_ADDR register (0x4897 D004)

    6.VIP_LIST_ATTR register (0x4897 D008) bit19 RDY bit does not become 1

    How do I set the VIP_LIST_ATTR [19] RDY bit to 1 to load the Descriptor?

    Which of the above #defines should be used with AM5716?

    Best Regards,

    M.Ohhashi