66AK2L06: C66x CorePac Primary Interrupt #17 (PCIE_0_INT4_PLUS_N)

Hi Yordan,

Thank you for the answer.

Yordan Kovachev said:

You cannot map it to both C66x CorePac & ARM CorePac interrupt controllers simultaneously.

This is very strange. Because I can handle my MSI interrupt from CIC0 as secondary interrupt to C66X CorePac. I've dumped raw interrupts status from CIC0 registers and found that PCIE_0_INT5 is continuously triggering an event. From my understanding, MSI0 should map to PCIE_0_INT4 (event #279), not PCIE_0_INT5 (event #280). Maybe this is our hardware issue, which generates MSI1 instead of MSI0. But on the Linux side I call

err = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
pci_request_irq(pci_dev, 0, msi_handler, NULL, dev, "msi%i", 0);

to allocate and handle MSI0 interrupt. And I thought that this will map to single MSI0. Can you confirm that CIC0 PCIE_0_INT4 (table 7-24 of datasheet) maps to MSI0?

Looking at PCIe user guide, I think that I was wrong in my first assumption with PCIE_0_INT4_PLUS_N. It should be rewritten as:

• MSI[0,4,8,12] for core #0
• MSI[1,5,9,13] for core #1
• MSI[2,6,10,14] for core #2
• MSI[3,7,11,15] for core #3

Can you give some explanation about PCIE_0_INT4_PLUS_N?

Best Regards,
Yurii

Hi,

Sorry, for the confusion, but to clear things out:

You are running linux on ARM and RTOS on DSP, right? And you want to trigger PCIE irq which should be handled by both ARM IRQ controller & DSP IRQ controller (have irq handler on both sides Linux & RTOS) at the same time?

I was answering assuming you want to handle the interrupt with both arm & dsp irq controllers, and I see that you just want to receive (read irqregisters) at the same time, right (?); and maybe caused a confusion with my initial reply.

Best Regards,
Yordan

Yordan,

Yordan Kovachev said:

You are running linux on ARM and RTOS on DSP, right?

I'm running Linux on ARM and bare metal on DSP (core #0 only for now). I boot DSP core #0 with simple driver (not mpmcl) which is able to mmap DSP's L2 and handles reset with syscon. Firmware is loaded from userspace by means of misc device (as in SDK).

Yordan Kovachev said:

And you want to trigger PCIE irq which should be handled by both ARM IRQ controller & DSP IRQ controller (have irq handler on both sides Linux & RTOS) at the same time?

Exactly. And I've even managed to achieve this by routing MSI interrupt through CIC0. With little confusion about MSI interrupt to CIC0 system event mapping (as described in previous post).

Best Regards,
Yurii

PS. I've made some edits in my previous before your reply.

Yordan Kovachev said:

I was answering assuming you want to handle the interrupt with both arm & dsp irq controllers

I want to receive MSI interrupts on both ARM and DSP. But MSI interrupt handling (e.g. writing MSIn_IRQ_STATUS and IRQ_EOI registers) is done by ARM side in keystone-pcie driver.

Hi lding,

Thank you for the answer, PCIE_0_INT4_PLUS_N purpose is completely clear now.

The only thing I can't figure out is that why our driver handles MSI1.

pci_alloc_irq_vectors(pci_dev, 1, 1, PCI_IRQ_MSI);
pci_request_irq(pci_dev, 0, &msi_handler, NULL, dev, "msi%i", 0);

From my point of view the code above should handle MSI0 only because we allocate one vector.

But msi_handler get called when I write 1 to MSI_IRQ register. And writing 0 does not trigger interrupt handler.

Best Regards,
Yurii

Hi Eric,

I have some problems understanding endpoint's MSI generation algorithm.

For example, Message Data register in EP configuration is programmed to 0x04.

Endpoint writes 0x04 to address 0x21800054. MSI0 is generated by hardware and caught by Linux driver code (and I can also simulate it by writing 0x04 to MSI_IRQ reg).

But I observe that no MSI0 (system event #279) is generated in CIC0. And it is only generated when I write 0x00 to MSI_IRQ register with devmem utility.

Best Regards,
Yurii

Eric,

We have K2L as RC and Xilinx FPGA as endpoint (using 7 Series Integrated Block for PCI Express v3.0).

lding said:

MSI_IRQ is already 0x2180_0054 on PCIE 0, what is the difference between two trials?

There is no difference, it was my lack of understanding.

lding said:

Let's assume the 0x04 landed at the RC side's MSI_IRQ, which MSIx_IRQ_STATUS_RAW (where x=0,1 .... 7) get set and what bit?

I've disabled all MSI interrupts with MSIx_IRQ_ENABLE_CLR registers and devmem. Looking at MSIx_IRQ_STATUS_RAW it seems that MSI4_IRQ_STATUS_RAW[0] bit is set and MSI4 generated, as per PCIe datasheet. There is some problem in MSI Data register setup for EP. Linux kernel writes 0x04 (i.e. number of vectors allocated) instead of 0x00.

I think that this issue is resolved, thank you. Now I'll look for some way to customize MSI Data register setup.

Best Regards,
Yurii