66AK2H12: Changing bus priorities in multicore app

Hi,

For the data, L2 to DDR is faster with L2 cached vs L2 is non-cached, this is expected as DDR3 is cached inside L2, see the cache user guide http://www.ti.com/lit/ug/sprugy8/sprugy8.pdf. Figure 1-3 C66x Cache Memory Architecture.

For the MDMA, the L2 <--------->XMC<------->MDMA<-------->MSMC<------>SES<------>DDR, the CSL_XMC_setMDMAPriority controls the bus priority with 0 highest and 7 the lowest, this also explains your observation in L2 cached with different Priorities, cores have a higher priority has faster throughput.

Regards, Eric

Thank you for your answer. As you can also notice when L2 cache is disabled, priority difference has no effect on throughput measurements. It is always around 103 MB/s. Why does this behavior occur?

Best,

samseytani

Thank you, finally do you have a technical document about the bus architecture of this Soc? ı couldnt  find it on web.

Regards,samseytani

On the there is a note that is;

NOTE: The above is more prominent for the 32 bit buses. The 64 bit buses are capable, to some extent, of issuing multiple outstanding read and write commands. For details on the buses, please refer to the section on Interconnect Buses in the c66x SoC Architecture Overview article.

Where is this article exactly?

Thanks.