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  • TI Thinks Resolved

K2GICE: K2GICE as pcie root complex

Intellectual 640 points

Replies: 1

Views: 39

Part Number: K2GICE

Hi

Is it possible to use k2gice as on pcie root complex by providing external clock via pcie connector and taking account the mixed transit and recieve lines or is there other reasons why this usage would not be possible.

BR

Tommi Mehtonen

  • Guru 80525 points

    Hi,

    Here is the K2G ICE EVM info landing page: http://www.ti.com/tool/K2GICE#technicaldocuments. You can find the EVM schematic and user guide: http://www.ti.com/lit/ug/spruie3/spruie3.pdf

    From user guide, it says "Although the K2G can be configured as a PCIE root-complex or endpoint, the K2G ICE only supports PCIE endpoint operations. The PCIE reference clock is only provided by the PCIE connector". 

    Also from user guide:

    2.3 Clocking

    The K2G ICE EVM derives all internal clocks, with the exception of the PCIE_CLK, from a single clock input. That clock input can be either the internal oscillator using crystal Y1, or an external clock generator connected to SYS_CLK_P/N. The PCIE clock is only present if the K2G EVM is inserted into a PCIE backplane.

    2.11 PCIE Edge Connector

    The K2G ICE includes a PCIE x1 edge connector as defined by the PCI Express Electromechanical Specification, Rev 2.0. While the edge connector and the board thickness are compatible with that standard, the K2G ICE was not designed to meet all the requirements for the Electromechanical specification, and is not designed to fit into a standard PC chassis. No I/O bracket is available, and the EVM is not compliant with the PCB form factor or component height restrictions.

    Although the K2G can be configured as a PCIE root-complex or endpoint, the K2G ICE only supports PCIE endpoint operations. The PCIE reference clock is only provided by the PCIE connector. No accesses to the PCIE portion of the K2G SOC should be performed unless a PCIE reference clock is present on the PCIE edge connector.

    3.3.5 PCIe Edge Connector (J7)

    The K2G ICE includes a x1 PCI Express endpoint connector capable of insertion into a PCI Express backplane connector. The K2G ICE is not compliant with the PCI Express Card Electromechanical pecification and is not designed to be inserted into a personal computer. The K2G ICE does not include an onboard 100-MHz PCIe reference clock. If the PCIe interface is active, a 100-MHz clock must be present on pins A13 and A14 for proper operation. While the K2G SoC can support both root complex and endpoint operation, this EVM is only designed to act as an endpoint.

    The PCIe backplane specification includes +12 V and +3.3 V to power cards inserted into the connector. The +12 V from the PCIe backplane can be used to power the K2G ICE. If +12 V is present on the backplane connector, there is no need to connect a power source to the DC jack (J6). If both voltage sources are present, the power supply uses the higher of the two voltages.

    So, if you want to modify this EVM, it is possible to use it as PCIE RC. I'm from the  software side, at least you need provide +12V and +3.3V power supply driving to the PCIE edge connector, provide reference clock to the PCIE module and drive the clock to the edge connector, also latch the PERST pin for reset.

    TI can't support you for hardware modification or be reliable for any damage it may cause.

    Regards, Eric

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