66AK2G12: Datasheet and TRM clarifications

Hi Darren,

- Does AUD0SC_IN need a pulldown?

AUDOSC has a strong pulldown if the pin is disabled. A pull down should not be needed if you are not using the pin.

- The datasheet says ball T1 (UART0_TXD) requires a pulldown if used.  Can you confirm, since it's an output?

I didn't see this comment in the data manual.  Can you point to where you saw it?

- The datasheet says DDR3_CBQS_P should be pulled LOW if unused.  Can you confirm?

- The datasheet says DDR3_CBQS_N should be pulled HIGH if unused.  Can you confirm?  Are these two the right way around?

The intent is to hold these signals in a steady inactive state.  The pulling resistors specified will do that.

- The datasheet says PORn must transition high a maximum of 2 ms after CVDD/CVDD1.  Should that be a minimum rather than maximum?  If it's a maximum, it would be nearly impossible to satisfy the SYSOSC_IN  requirement of clock being stable for 2 ms prior to PORn being released.

This is confusing.  There are two specifications that are in conflict.  First is that the clock must be stable for 2ms before PORn is released. This is the important spec.  The 2ms maximum you noted is specifying that the PORn should not be held low for extended periods of time after CVDD is valid.  This is included to be sure that customers are not using the reset signal to keep the SoC in a reset state for long periods of time to save power or delay startup.  The SYSCLK_IN will stabilize after CVDD is applied and the PORn signal should go high 2ms after the clock is present.  

Figures 5-3 and 5-4 do not show the timing of RESET_FULLn, RESETn, LRESETn, LRESETNMIENn and NMIn.  Where do we find these details?

- Timing for RESET_FULLn should follow PORn.  Timing for the LRESETn should follow RESETn.  Let me check on the other two signal.

Regards, Bill

Bill,

Thank you for the feedback so far.  I have to correct my typo on the T1 question.  I should have wrote "if unused".  The customer has pointed to table 4-29 where the pull-down is specified.

For the last question, can you provide the timing requirement for RESETn?  Figure 5-3, section 5.9.1.1, the only reset signal shown is PORn.

Thanks,

Darren

Hi Bill,

Any more feedback on this?

Thanks,

Darren

Hi Darren,

The RESETN timing is shown in figure 5-6 of the data manual.  RESETN is not included in the power up sequencing document  because it should not be active during PORz.  RESETN should be pulled high to the 3.3V IO supply and should remain high until after the part is out of reset.  Once it is out of reset the RESETN signal may be used if needed.

I'm still searching for an answer on T1.

Regards, Bill